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| Active-Semi FEATURES * ActivePathTM Li+ Charger with System Power Selection * Six Integrated Regulators - 1.3A High Efficiency Step-Down DC/DC - 1.0A High Efficiency Step-Down DC/DC - 0.55A High Efficiency Step-Down DC/DC - 2x360mA Low Noise, High PSRR LDOs - 30mA RTC LDO / Backup Battery Charger * I2CTM Serial Interface * Minimal External Components ACT8810 Rev 4, 01-Oct-09 Eight Channel ActivePathTM Power Management IC GENERAL DESCRIPTION The patent-pending ACT8810 is a complete, cost effect tive, highly-efficient ActivePMUTM power management solution that is ideal for a wide range of high performance portable handheld applications such as personal navigation devices (PNDs). This device integrates the ActivePathTM complete battery charging and management system with six power supply channels. The ActivePath architecture automatically selects the best available input supply for the system. If the external input source is not present or the system load current is more than the input source can provide, the ActivePath supplies additional current from the battery to the system. The charger is a complete, thermallyregulated, stand-alone single-cell linear Li+ charger that incorporates an internal power MOSFET. REG1, REG2, and REG3 are three independent, fixed-frequency, current-mode step-down DC/DC converters that output 1.3A, 1.0A, and 0.55A, respectively. REG4 and REG5 are high performance, low-noise, low-dropout linear regulators that output up to 360mA each. REG6 is a RTC LDO that outputs up to 30mA for a real time clock. Finally, an I2C serial interface provides programmability for the DC/DC converters and LDOs. The ACT8810 is available in a tiny 5mm x 5mm 40pin Thin-QFN package that is just 0.75mm thin. * Compatible with USB or AC-Adapter Charging * 5mm x 5mm, Thin-QFN (TQFN55-40) Package - Only 0.75mm Height - RoHS Compliant APPLICATIONS * Personal Navigation Devices * Portable Media Players * Smart Phones SYSTEM BLOCK DIAGRAM CHG_IN CHGLEV DCCC ISET ACIN nSTAT TH BTR nPBIN nIRQ nRSTO SCL SDA ON1 ON2 ON3 VSEL Battery Programmable Up to 1A VSYS REG1 Step-Down DC/DC REG2 Step-Down DC/DC REG3 Step-Down DC/DC System Control REG4 LDO REG5 LDO OUT1 Adjustable, or 0.8V to 4.4V Up to 1.3A OUT2 Adjustable, or 0.8V to 4.4V Up to 1.0A OUT3 Adjustable, or 0.8V to 4.4V Up to 0.55A OUT4 0.9V to 3.3V Up to 360mA OUT5 0.9V to 3.3V Up to 360mA OUT6 0.9V to 3.3V Up to 30mA ActivePathTM & Single-Cell Li+ Battery Charger ACT8810 Active PMU TM REG6 RTC_LDO Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of Philips Electronics. -1- www.active-semi.com Copyright (c) 2009 Active-Semi, Inc. Active-Semi TABLE OF CONTENTS ACT8810 Rev 4, 01-Oct-09 GENERAL INFORMATION ..........................................................................................P. 01 Functional Block Diagram ...................................................................................................... p. 03 Ordering Information .............................................................................................................. p. 04 Pin Configuration .................................................................................................................... p. 04 Pin Descriptions ..................................................................................................................... p. 05 Absolute Maximum Ratings.................................................................................................... p. 07 SYSTEM MANAGEMENT ...........................................................................................P. 08 Register Descriptions ............................................................................................................. p. 08 I2C Interface Electrical Characteristics ................................................................................... p. 09 Electrical Characteristics ........................................................................................................ p. 10 Register Descriptions ............................................................................................................. p. 11 Typical Performance Characteristics...................................................................................... p. 12 Functional Description ............................................................................................................ p. 13 STEP-DOWN DC/DC CONVERTERS ..........................................................................P. 17 Electrical Characteristics ........................................................................................................ p. 17 Typical Performance Characteristics...................................................................................... p. 20 Register Descriptions ............................................................................................................. p. 22 Functional Description ............................................................................................................ p. 28 LOW-DROPOUT LINEAR REGULATORS ..................................................................P. 31 Electrical Characteristics ........................................................................................................ p. 31 Typical Performance Characteristics...................................................................................... p. 33 Register Descriptions ............................................................................................................. p. 34 Functional Description ............................................................................................................ p. 36 RTC LOW-DROPOUT LINEAR REGULATOR ............................................................P. 37 Electrical Characteristics ........................................................................................................ p. 37 Register Descriptions ............................................................................................................. p. 38 Functional Description ............................................................................................................ p. 39 ActivePathTM CHARGER .............................................................................................P. 40 Electrical Characteristics ........................................................................................................ p. 40 Typical Performance Characteristics...................................................................................... p. 42 Functional Description ............................................................................................................ p. 44 PACKAGE INFORMATION ..........................................................................................P. 52 Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of Philips Electronics. -2- www.active-semi.com Copyright (c) 2009 Active-Semi, Inc. Active-Semi FUNCTIONAL BLOCK DIAGRAM BODY SWITCH ACT8810 Rev 4, 01-Oct-09 (Optional) AC Adaptor USB Active-Semi ACT8810 BODY SWITCH CHG_IN Up to 12V DCCC VSYS System Supply BAT ACIN ActivePath Control 100A CURRENT SENSE Li+ Battery VSYS nSTAT CHARGE STATUS + TH VOLTAGE SENSE PRECONDITION THERMAL REGULATION 2.9V 110C BTR ISET VSYS CHGLEV OUT1 Charge Control VP1 SW1 REG1 To VSYS nRSTO OUT1 OUT1 GP1 VSYS nPBIN PUSH BUTTON OUT1 REG2 nIRQ VP2 To VSYS SW2 OUT2 OUT2 GP2 VP3 SCL SW3 REG3 SDA ON1 To VSYS System Control OUT3 OUT3 GP3 INL OUT4 OUT4 OUT5 OUT5 OUT6 OUT6 ON2 To VSYS ON3 REG4 LDO REG5 LDO REG6 RTC_LDO VSEL REFBP Reference GA EP Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of Philips Electronics. -3- www.active-semi.com Copyright (c) 2009 Active-Semi, Inc. Active-Semi ORDERING INFORMATION PART NUMBER ACT8810QJ1C1-T ACT8810QJ213-T ACT8810QJ3EB-T ACT8810QJ45D-T ACT8810QJ50F-T ACT8810 Rev 4, 01-Oct-09 VOUT1/VSTBY1 3.3V/3.3V 1.2V/1.2V 3.3V/3.3V 3.3V/3.3V 1.2V/1.2V VOUT2/VSTBY2 VOUT3/VSTBY3 VOUT4 VOUT5 VOUT6 CONTROL SEQUENCE 1.1V/1.2V 1.8V/1.8V 1.2V/1.2V 1.8V/1.8V 3.3V/3.3V 1.2V/1.2V 1.0V/1.0V 1.8V/1.8V 1.3V/1.3V 1.8V/1.8V 1.2V 3.3V 1.5V 1.2V 3.3V 2.8V 1.2V 2.8V 3.3V 1.8V 3.3V 3.0V 3.3V 3.3V 3.0V Sequence A Sequence B Sequence C Sequence D Sequence E PACKAGING DETAILS ACT8810QJ###-T PACKAGE TQFN55-40 PINS 40 TEMPERATURE RANGE -40C to +85C PACKING TAPE & REEL : All Active-Semi components are RoHS Compliant and with Pb-free plating unless specified differently. The term Pb-free means semiconductor products that are in compliance with current RoHS (Restriction of Hazardous Substances) standards. : To select VSTBYx as a output regulation voltage of REGx, tie VSEL to VSYS or a logic high. : Refer to the Control Sequence section for more information. PIN CONFIGURATION TOP VIEW CHGLEV nRSTO REFBP nSTAT OUT4 nIRQ ON2 INL GA GA TH DCCC BTR ACIN BAT BAT VSYS VSYS CHG_IN ISET OUT5 OUT6 VP3 Active-Semi ACT8810 EP SW3 GP3 OUT3 nPBIN SDA SCL ON3 VSEL ON1 Thin - QFN (TQFN55-40) OUT2 VP2 SW2 GP2 GP1 SW1 VP1 OUT1 Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of Philips Electronics. -4- www.active-semi.com Copyright (c) 2009 Active-Semi, Inc. Active-Semi PIN DESCRIPTIONS PIN 1 ACT8810 Rev 4, 01-Oct-09 NAME TH DESCRIPTION Temperature Sensing Input. Connect to battery thermistor. TH is pulled up with a 100A current internally. See the Battery Temperature Monitoring section for more information. Dynamic Charging Current Control. Connect a resistor to set the dynamic charging current control point. A internal 100A current source sets up a voltage that is used to compare with VSYS and dynamically scale the charging current to maintain VSYS regulation. See the Dynamic Charge Current Control section for more information. Safety Timer Program Pin. The resistance between this pin and GA determines the timers timeout values. See the Charging Safety Timers section for more information. AC Adaptor Detect. Detects presence of a wall adaptor and automatically adjusts the charge current to the maximum charge current level. Do not leave ACIN floating. Battery Charger Output. Connect this pin directly to the battery anode (+ terminal) System Output Pin. Bypass to GA with a 10F or larger ceramic capacitor. 2 DCCC 3 4 5, 6 7, 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 BTR ACIN BAT VSYS Power Input for the Battery Charger. Bypass CHG_IN to GA with a capacitor placed as close to the CHG_IN IC as possible. The battery charger are automatically enabled when a valid voltage is present on CHG_IN. See the CHG_IN Bypass Capacitor Selection section for more information. ISET VSEL ON1 OUT2 VP2 SW2 GP2 GP1 SW1 VP1 OUT1 ON3 SCL SDA Charge Current Set. Program the maximum charge current by connecting a resistor (RISET) between ISET and GA. See the Charger Current Programming section for more information. Step-Down DC/DCs Output Voltage Selection. Drive to logic low to select default output voltage. Drive to logic high to select secondary output voltage. See the Output Voltage Selection Pin section for more information. Independent Enable Control Input for REG1. Drive ON1 to VSYS or to a logic high for normal operation, drive to GA or a logic low to disable REG1. Do not leave ON1 floating. Output Feedback Sense for REG2. Connect this pin directly to the output node to connect the internal feedback network to the output voltage. Power Input for REG2. Bypass to GP2 with a high quality ceramic capacitor placed as close as possible to the IC. Switching Node Output for REG2. Connect this pin to the switching end of the inductor. Power Ground for REG2. Connect GA, GP1, GP2 and GP3 together at a single point as close to the IC as possible. Power Ground for REG1. Connect GA, GP1, GP2 and GP3 together at a single point as close to the IC as possible. Switching Node Output for REG1. Connect this pin to the switching end of the inductor. Power Input for REG1. Bypass to GP1 with a high quality ceramic capacitor placed as close as possible to the IC. Output Feedback Sense for REG1. Connect this pin directly to the output node to connect the internal feedback network to the output voltage. Enable Control Input for REG3. Drive ON3 to a logic high for normal operation, drive to GA or a logic low to disable REG3. Do not leave ON3 floating. Clock Input for I2C Serial Interface. Data Input for I2C Serial Interface. Data is read on the rising edge of SCL. Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of Philips Electronics. -5- www.active-semi.com Copyright (c) 2009 Active-Semi, Inc. Active-Semi PIN DESCRIPTIONS CONT'D PIN 24 ACT8810 Rev 4, 01-Oct-09 NAME nPBIN DESCRIPTION Master Enable Input. Drive nPBIN to GA through a 100k resistor to enable the IC, drive nPBIN directly to GA to assert a Hard-Reset condition. Refer to the System Startup & Shutdown and Control Sequence sections for more information. nPBIN is internally pulled up to VSYS through a 50k resistor. Output Feedback Sense for REG3. Connect this pin directly to the output node to connect the internal feedback network to the output voltage. Power Ground for REG3. Connect GA, GP1, GP2, and GP3 together at a single point as close to the IC as possible. Switching Node Output for REG3. Connect this pin to the switching end of the inductor. Power Input for REG3. Bypass to GP3 with a high quality ceramic capacitor placed as close as possible to the IC. RTC LDO Output Voltage. Capable of delivering up to 30mA of output current. Output Voltage for REG5. Capable of delivering up to 360mA of output current. The output is discharged to GA with 1k when disabled. Power Input for REG4, REG5, and REG6. Bypass to GA with a high quality ceramic capacitor placed as close as possible to the IC. Output Voltage for REG4. Capable of delivering up to 360mA of output current. The output is discharged to GA with 1k when disabled. Active-Low Open-Drain Charger Status Output. nSTAT has a 5mA (typ) current limit, allowing it to directly drive an indicator LED without additional external components. To generate a logic-level output, connect nSTAT to an appropriate supply voltage (typically VSYS) through a 10k or greater pull-up resistor. See the Charge Status Indication section for more information. Independent Enable Control Input for REG2. Drive ON2 to a logic high for normal operation, drive to GA or a logic low to disable REG2. Do not leave ON2 floating. Analog Ground. Connect GA directly to a quiet ground node. Connect GA, GP1, GP2, and GP3 together at a single point as close to the IC as possible. Reference Noise Bypass. Connect a 0.01F ceramic capacitor from REFBP to GA. This pin is discharged to GA in shutdown. Open-Drain Reset Output. nRSTO asserts low whenever REG1 is out of regulation, and remains low for 260ms (typ) after REG1 reaches regulation. Open-Drain Interrupt Output. nIRQ asserts any time nPBIN is asserted or an unmasked fault condition exists. See the nIRQ Output section for more information. Charging State Select Input. 25 26 27 28 29 30 31 32 OUT3 GP3 SW3 VP3 OUT6 OUT5 INL OUT4 33 nSTAT 34 35, 37 36 38 39 ON2 GA REFBP nRSTO nIRQ 40 When ACIN = 0 charge current is internally set; Drive CHGLEV to a logic-high for high-current USB charging mode (maximum charge current is 500mA), drive CHGLEV to a logic-low for low-current CHGLEV USB charging mode (maximum charge current is 100mA). When ACIN = 1 charge current is externally set by RISET; Drive CHGLEV to a logic-high to for highcurrent charging mode (ICHG = K x 1000/RISET (mA) where K = 640), drive CHGLEV to a logic-low for low-current charging mode (ICHG = K x 500/RISET (mA) where K = 640). Do not leave CHGLEV floating. EP EP Exposed Pad. Must be soldered to ground on the PCB. Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of Philips Electronics. -6- www.active-semi.com Copyright (c) 2009 Active-Semi, Inc. Active-Semi ABSOLUTE MAXIMUM RATINGS PARAMETER CHG_IN to GA t < 1ms and duty cycle <1% Steady State VP1 to GP1, VP2 to GP2, VP3 to GP3 BAT, VSYS, INL to GA SW1, OUT1 to GP1 SW2, OUT2 to GP2 SW3, OUT3 to GP3 ON1, ON2, ON3, ISET, ACIN, VSEL, DCCC, CHGLEV, TH, SCL, SDA, REFBP, nIRQ, nRSTO, nSTAT, BTR, nPBIN to GA OUT4, OUT5, OUT6 to GA Operating Ambient Temperature Maximum Junction Temperature Maximum Power Dissipation TQFN55-40 (Thermal Resistance JA = 30oC/W) Storage Temperature Lead Temperature (Soldering, 10 sec) ACT8810 Rev 4, 01-Oct-09 VALUE -0.3 to +18 -0.3 to +14 -0.3 to +6 -0.3 to +6 -0.3 to (VVP1 +0.3) -0.3 to (VVP2 +0.3) -0.3 to (VVP3 +0.3) -0.3 to +6 -0.3 to (VINL +0.3) -40 to 85 125 2.7 -65 to 150 300 UNIT V V V V V V V V V C C W C C : Do not exceed these limits to prevent damage to the device. Exposure to absolute maximum rating conditions for long periods may affect device reliability. Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of Philips Electronics. -7- www.active-semi.com Copyright (c) 2009 Active-Semi, Inc. Active-Semi REGISTER DESCRIPTIONS Table 1: Global Register Map OUTPUT SYS REG1 REG1 REG1 REG1 REG2 REG2 REG2 REG2 REG3 REG3 REG3 REG3 REG4 REG4 REG5 REG6 KEY: R: Read-Only bits. No Default Assigned. V: Default Values Depend on Voltage Option. Default Values May Vary. ACT8810 Rev 4, 01-Oct-09 SYSTEM MANAGEMENT ADDRESS HEX 06h 10h 11h 12h 13h 20h 21h 22h 23h 30h 31h 32h 33h 40h 43h 41h 42h A7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A6 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 A5 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 A4 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 A3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 A0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 D7 R R R R R R R R R R R R R 1 R 1 R DATA (DEFAULT VALUE) D6 R R R R V R R R V R R R V R R R R D5 R V R R V V R R V V R R V 1 R 1 R D4 0 V R R V V R R V V R R V V R V V D3 R V R R V V R R V V R R V V R V V D2 R V R 0 V V R 0 V V R 0 V V R V V D1 1 V R R V V R R V V R R V V 0 V V D0 R V R 1 V V R 1 V V R 1 V V R V V Note: Addresses other than those specified in Table 1 may be used for factory settings. Do not access any registers other than those specified in Table 1. Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of Philips Electronics. -8- www.active-semi.com Copyright (c) 2009 Active-Semi, Inc. Active-Semi I2C INTERFACE ELECTRICAL CHARACTERISTICS (VVSYS = 3.6V, TA = 25C, unless otherwise specified.) ACT8810 Rev 4, 01-Oct-09 SYSTEM MANAGEMENT PARAMETER SCL, SDA Low Input Voltage SCL, SDA High Input Voltage SCL, SDA Leakage Current SDA Low Output Voltage SCL Clock Period, tSCL SDA Data In Setup Time to SCL High, tSU SDA Data Out Hold Time after SCL Low, tHD SDA Data Low Setup Time to SCL Low, tST TEST CONDITIONS VVSYS = 2.6V to 5.5V, TA = -40C to 85C VVSYS = 2.6V to 5.5V, TA = -40C to 85C MIN 1.55 TYP MAX UNIT 0.35 V V 1 A V s ns ns ns ns IOL = 5mA 2.5 100 300 Start Condition 100 100 0.3 SDA Data High Hold Time after Clock High, tSP Stop Condition Figure 1: I2C Serial Bus Timing tSCL SCL tST SDA IN tSU tSP tHD SDA OUT Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of Philips Electronics. -9- www.active-semi.com Copyright (c) 2009 Active-Semi, Inc. Active-Semi ELECTRICAL CHARACTERISTICS (VVSYS = 3.6V, TA = 25C, unless otherwise specified.) ACT8810 Rev 4, 01-Oct-09 WLED BIAS DC/DC CONVERTER (REG3) PARAMETER Input Voltage Range UVLO Threshold Voltage UVLO Hysteresis VSYS Supply Current VSYS Shutdown Current Voltage Reference Oscillator Frequency Logic High Input Voltage Logic Low Input Voltage Leakage Current nPBIN Internal Pull-up Resistance Low Level Output Voltage nRSTO Delay Thermal Shutdown Temperature Thermal Shutdown Hysteresis VSYS Rising TEST CONDITIONS MIN 2.6 2.35 TYP 2.5 100 70 30 MAX 5.5 2.6 UNIT V V mV A A VSYS Falling ONx = VSYS ONx = GA, Not Charging 1.24 1.35 ON1, ON2, ON3, VSEL ON1, ON2, ON3, VSEL VON1 = VON2 = VON3 = VVSEL = VnIRQ = VnRSTO = 4V 1.4 1.25 1.6 1.26 1.85 V MHz V 0.4 1 50 V A k V ms C C nIRQ, nRSTO. Sinking 10mA 0.3 260 Temperature rising Temperature decreasing 160 20 Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of Philips Electronics. - 10 - www.active-semi.com Copyright (c) 2009 Active-Semi, Inc. Active-Semi REGISTER DESCRIPTIONS Note: See Table 1 for default register settings. ACT8810 Rev 4, 01-Oct-09 SYSTEM MANAGEMENT Table 2: Control Register Map ADDRESS 06h DATA D7 R D6 R D5 R D4 W/E D3 R D2 R D1 nPBMASK D0 PBSTAT R: Read-Only bits. Default Values May Vary. W/E: Write-Exact bits. Read/Write bits which must be written exactly as specified in Table 1. Table 3: Control Register Bit Descriptions ADDRESS 06h NAME PBSTAT BIT [0] ACCESS R/W FUNCTION Push Button Status 0 1 0 1 DESCRIPTION De-assert Asserted Masked Not Mask READ ONLY WRITE-EXACT READ ONLY 06h 06h 06h 06h nPBMASK [1] [3:2] [4] [7:5] R/W R W/E R Push Button Interrupt Mask Option Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of Philips Electronics. - 11 - www.active-semi.com Copyright (c) 2009 Active-Semi, Inc. Active-Semi TYPICAL PERFORMANCE CHARACTERISTICS (VVSYS = 3.6V, TA = 25C, unless otherwise specified.) ACT8810 Rev 4, 01-Oct-09 SYSTEM MANAGEMENT Oscillator Frequency vs. Temperature 1.71 ACT8810-001 Oscillator Frequency (MHz) 1.68 1.65 1.62 1.59 1.56 1.53 1.50 -40 -20 0 20 40 60 85 Temperature (C) Shutdown Current vs. Temperature 26 ACT8810-002 ON1 = ON2 = ON3 = GA Shutdown Current (A) VVSYS = 4.2V 24 VVSYS = 3.6V 22 VVSYS = 3.2V 20 -40 -20 0 20 40 60 85 Temperature (C) Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of Philips Electronics. - 12 - www.active-semi.com Copyright (c) 2009 Active-Semi, Inc. Active-Semi FUNCTIONAL DESCRIPTION General Description The ACT8810 offers a wide array of system management functions that allow it to be configured for optimal performance in a wide range of applications. ACT8810 Rev 4, 01-Oct-09 SYSTEM MANAGEMENT I2C Serial Interface At the core of the ACT8810's flexible architecture is an I2C interface that permits optional programming capability to enhance overall system performance. To ensure compatibility with a wide range of system processors, the ACT8810 uses standard I2C commands; I2C write-byte commands are used to program the ACT8810, and I2C read-byte commands are used to read the ACT8810's internal registers. The ACT8810 always operates as a slave device, and is addressed using a 7-bit slave address followed by an eighth bit, which indicates whether the transaction is a read-operation or a write-operation, [1011010x]. SDA is a bi-directional data line and SCL is a clock input. The master initiates a transaction by issuing a START condition, defined by SDA transitioning from high to low while SCL is high. Data is transferred in 8-bit packets, beginning with the MSB, and is clocked-in on the rising edge of SCL. Each packet of data is followed by an "Acknowledge" (ACK) bit, used to confirm that the data was transmitted successfully. For more information regarding the I2C 2-wire serial interface, go to the NXP website: http://www.nxp.com process is completely software-controlled, a typical shutdown sequence proceeds as follows: The second assertion of nPBIN asserts nPBIN and interrupts the microprocessor, which then initiates an interrupt service routine to reveal that nPBIN has been asserted. If there is no input to the charger, then the microprocessor disables each regulator according to the sequencing requirements of the system, then the system will finally be disabled when each of ON1, ON2, and ON3 have been deasserted. nPBIN Input ACT8810's nPBIN pin is a dual-function pin, combining system enable/disable control with a hardware reset function. Refering to Figure 2, the two pin functions are obtained by asserting this pin low, either through a direct connection or through a 100k resistor, as described below. In most applications, nPBIN will be driven through a 100k resistor. When driven in this way, nPBIN initiates system startup or shutdown, as described in the System Startup and Shutdown section. When a hardware-reset function is desired, nPBIN may also be driven directly to GA. In this case, nRSTO is immediately asserted low and remains low until nPBIN is de-asserted and the reset timeout period expires. This provides a hardware-reset function, allowing the system to be manually reset if the system processor locks up. Although a typical application will use momentary switches to drive nPBIN, as shown in Figure 2, nPBIN may also be driven by other sources, such as a GPIO or other logic output. Figure 2: nPBIN Input System Startup and Shutdown Startup Sequence The ACT8810 features a flexible enable architecture that allows it to support a variety of push-button enable/disable schemes. Although other startup routines are possible, ACT8810 provides three typical startup and shutdown processes proceed as shown in Control Sequence section. Shutdown Sequence Once a successful power-up routine is completed, a shutdown process may be initiated by asserting nPBIN a second time, typically as the result of pressing the push-button. Although the shutdown Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of Philips Electronics. Enable/Disable Inputs (ON1, ON2 and ON3) The ACT8810 provides three manual enable/disable inputs, ON1, ON2 and ON3, which - 13 www.active-semi.com Copyright (c) 2009 Active-Semi, Inc. Active-Semi FUNCTIONAL DESCRIPTION CONT'D enable and disable REG1, REG2, and REG3, respectively. Once the system is enabled, the system will remain enabled until all of ON1, ON2, and ON3 have been de-asserted. See the Control Sequence section for more information. ACT8810 Rev 4, 01-Oct-09 SYSTEM MANAGEMENT Power-On Reset Output nRSTO is an open-drain output which asserts low upon startup or when nPBIN is driven directly to GA, and remains asserted low until the 260ms (default) power-on reset timer has expired. Connect a 10k or greater pull-up resistor from nRSTO to an appropriate voltage supply. nIRQ Output nIRQ is an open-drain output that asserts low any time startup or an unmasked fault condition exists. When asserted, nIRQ remains low until the microprocessor polls the ACT8810's I2C interface. The ACT8810 supports a variety of other fault conditions, which may each be optionally unmasked via the I2C interface. For more information about the available fault conditions, refer to the appropriate sections of this datasheet. Connect a pull-up resistor from nIRQ to an appropriate voltage supply. nIRQ is typically used to drive the interrupt input of the system processor, and is useful in a variety of software-controlled enable/disable control routines. ACT8810QJ1## begins its system startup procedure by enabling REG1. When REG1 reaches 94% of its final regulation voltage, ACT8810QJ1## automatically turns on REG4 and REG5 and nRSTO is asserted low, holding the microprocessor in reset for a user-selectable reset period of 260ms. If VOUT1 is within 6% of its regulation voltage when the reset timer expires, the nRSTO is de-asserted, and the microprocessor can begin its power-up sequence. Once the power-up routine is successfully completed, the system remains enabled after the push-button is released as long as the microprocessor asserts any one of ON1, ON2 or ON3, and REG4, REG5 may be enabled or disabled via the I2C interface. This start-up procedure requires that the pushbutton be held until the microprocessor assumes control (by asserting any one of ON1, ON2, and ON3), providing protection against inadvertent momentary assertions of the pushbutton. If desired, longer "push-and-hold" times can be easily implemented by simply adding an additional time delay before asserting ON1, ON2, or ON3. If the microprocessor is unable to complete its power-up routine successfully before the user lets go of the push-button, the ACT8810QJ1## automatically shuts itself down. Figure 3: Sequence A First Push Button nPBIN Assert Power-Hold Release Button Second Push System Button Shutdown Thermal Shutdown The ACT8810 integrates thermal shutdown protection circuitry to prevent damage resulting from excessive thermal stress, as may be encountered under fault conditions. This circuitry disables all regulators if the ACT8810 die temperature exceeds 160C, and prevents the regulators from being enabled until the IC temperature drops by 20C (typ). System Enable OUT1 ON1, ON2, ON3 OUT2, OUT3 OUT4, OUT5 Reset time Enable nRSTO nIRQ 260ms 94% of VOUT1 Control Sequence Sequence A The ACT8810QJ1## which is set with "sequence A", has a system startup is initiated whenever the following conditions occurs: 1) nPBIN is pushed low via 100k resistance, When ever this condition exists, the - 14 - Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of Philips Electronics. www.active-semi.com Copyright (c) 2009 Active-Semi, Inc. Active-Semi Sequence B The ACT8810QJ2## which is set with "sequence B", has a system startup is initiated whenever the following conditions occurs: 1) nPBIN is pushed low via 100k resistance, When ever this condition exists, the ACT8810QJ2## begins its system startup procedure by enabling REG1. When REG1 reaches 94% of its final regulation voltage, ACT8810QJ2## automatically turns on REG2 and REG3 and nRSTO is asserted low, holding the microprocessor in reset for a user-selectable reset period of 260ms. If VOUT1 is within 6% of its regulation voltage when the reset timer expires, the nRSTO is de-asserted, and the microprocessor can begin its power-up sequence. Once the power-up routine is successfully completed, the system remains enabled after the push-button is released as long as the microprocessor asserts any one of ON1, ON2 or ON3. REG4 and REG5 may be enabled if the microprocessor sets REG4.ON[] and REG5.ON[] to 1 via the I2C interface. In other case, REG4 and REG5 are disable. This start-up procedure requires that the pushbutton be held until the microprocessor assumes control (by asserting any one of ON1, ON2, and ON3), providing protection against inadvertent momentary assertions of the pushbutton. If desired, longer "push-and-hold" times can be easily implemented by simply adding an additional time delay before asserting ON1, ON2, or ON3. If the microprocessor is unable to complete its power-up routine successfully before the user lets go of the push-button, the ACT8810QJ2## automatically shuts itself down. Figure 4: Sequence B First Push Button nPBIN Assert Power-Hold Release Button Second Push System Button Shutdown ACT8810 Rev 4, 01-Oct-09 SYSTEM MANAGEMENT Sequence C The ACT8810QJ3## which is set with "sequence C", has a system startup is initiated whenever the following conditions occurs: 1) nPBIN is pushed low via 100k resistance, When ever this condition exists, the ACT8810QJ3## begins its system startup procedure by enabling REG1. When REG1 reaches 94% of its final regulation voltage, ACT8810QJ3## automatically turns on REG2, REG3, REG4, REG5 and nRSTO is asserted low, holding the microprocessor in reset for a user-selectable reset period of 260ms. If VOUT1 is within 6% of its regulation voltage when the reset timer expires, the nRSTO is de-asserted, and the microprocessor can begin its power-up sequence. Once the power-up routine is successfully completed, the system remains enabled after the push-button is released as long as the microprocessor asserts any one of ON1, ON2 or ON3, and REG4, REG5 may be enabled or disabled via the I2C interface. This start-up procedure requires that the pushbutton be held until the microprocessor assumes control (by asserting any one of ON1, ON2, and ON3), providing protection against inadvertent momentary assertions of the pushbutton. If desired, longer "push-and-hold" times can be easily implemented by simply adding an additional time delay before asserting ON1, ON2, or ON3. If the microprocessor is unable to complete its power-up routine successfully before the user lets go of the push-button, the ACT8810QJ3## automatically shuts itself down. Figure 5: Sequence C First Push Button nPBIN Assert Power-Hold Release Button Second Push System Button Shutdown System Enable System Enable OUT1 Enable Qualification ON1, ON2, ON3 OUT2, OUT3 REG4.ON[ ], REG5.ON[ ] OUT4, OUT5 Reset time Enable nRSTO nIRQ 260ms 94% of V OUT1 ~100ms OUT1 Enable Qualification ON1, ON2, ON3 OUT2, OUT3 OUT4, OUT5 Reset time Enable nRSTO nIRQ 94% of VOUT1 ~100ms 260ms Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of Philips Electronics. - 15 - www.active-semi.com Copyright (c) 2009 Active-Semi, Inc. Active-Semi Sequence D The ACT8810QJ4## which is set with "sequence D", has a system startup is initiated whenever the following conditions occurs: 1) nPBIN is pushed low via 100k resistance, When ever this condition exists, the ACT8810QJ4## begins its system startup procedure by enabling REG1, REG2, REG4, and REG5. When ACT8810QJ4## in the first enable, nRSTO is asserted low, holding the microprocessor in reset for a user-selectable reset period of 260ms. when the reset timer expires, the nRSTO is deasserted, and the microprocessor can begin its power-up sequence. Once the power-up routine is successfully completed, the system remains enabled after the push-button is released as long as the microprocessor asserts any one of ON1, ON2 or ON3, holding REG1, REG2, REG4, REG5, and enabling REG3. And any regulators could be enabled or disabled via the I2C interface. This start-up procedure requires that the pushbutton be held until the microprocessor assumes control (by asserting any one of ON1, ON2, and ON3), providing protection against inadvertent momentary assertions of the pushbutton. If desired, longer "push-and-hold" times can be easily implemented by simply adding an additional time delay before asserting ON1, ON2, or ON3. If the microprocessor is unable to complete its power-up routine successfully before the user lets go of the push-button, the ACT8810QJ4## automatically shuts itself down. Figure 6: Sequence D First Push Button nPBIN CHG_IN OR nPBIN ACT8810 Rev 4, 01-Oct-09 SYSTEM MANAGEMENT Sequence E The ACT8810QJ5## which is set with "sequence E", has a system startup is initiated whenever the following conditions occurs: 1) A valid input voltage is present at VIN, or 2) nPBIN is pushed low via 100k resistance, When ever this condition exists, the ACT8810QJ5## begins its system startup procedure by enabling REG1. When REG1 reaches 94% of its final regulation voltage, ACT8810QJ5## automatically turns on REG2, REG3, REG4, REG5 and nRSTO is asserted low, holding the microprocessor in reset for a user-selectable reset period of 260ms. If VOUT1 is within 6% of its regulation voltage when the reset timer expires, the nRSTO is de-asserted, and the microprocessor can begin its power-up sequence. Once the power-up routine is successfully completed, the system remains enabled after the push-button is released as long as the microprocessor asserts any one of ON1, ON2 or ON3, and REG4, REG5 may be enabled or disabled via the I2C interface. This start-up procedure requires that the pushbutton be held until the microprocessor assumes control (by asserting any one of ON1, ON2, and ON3), providing protection against inadvertent momentary assertions of the pushbutton. If desired, longer "push-and-hold" times can be easily implemented by simply adding an additional time delay before asserting ON1, ON2, or ON3. If the microprocessor is unable to complete its power-up routine successfully before the user lets go of the push-button or un-plug charger input, the ACT8810QJ5## automatically shuts itself down. Figure 7: Sequence E First Push Button Assert Power-Hold Release Button Second Push System Button Shutdown Assert Power-Hold Release Button Second Push Button System Shutdown System Enable OUT1, OUT2 OUT4, OUT5 ON1, ON2, ON3 OUT3 Reset time Enable 260ms System Enable OUT1 Enable Qualification ON1, ON2, ON3 OUT2, OUT3 OUT4, OUT5 Reset time Enable 260ms 94% of VOUT1 ~100ms nRSTO nIRQ nRSTO nIRQ Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of Philips Electronics. - 16 - www.active-semi.com Copyright (c) 2009 Active-Semi, Inc. Active-Semi ELECTRICAL CHARACTERISTICS (REG1) (VVSYS = 3.6V, TA = 25C, unless otherwise specified.) ACT8810 Rev 4, 01-Oct-09 STEP-DOWN DC/DC CONVERTERS PARAMETER VP1 Operating Voltage Range VP1 UVLO Threshold VP1 UVLO Hysteresis Quiescent Supply Current Shutdown Supply Current Output Voltage Accuracy Line Regulation Load Regulation Current Limit Oscillator Frequency PMOS On-Resistance NMOS On-Resistance SW1 Leakage Current Power Good Threshold Minimum On-Time TEST CONDITIONS Input Voltage Rising Input Voltage Falling MIN 2.9 2.7 TYP 2.8 85 130 MAX 5.5 2.9 UNIT V V mV 200 1 +2.1% +1.5% A A V %/V %/mA A REG1 is disabled, VVP1 = 4.2V VNOM1 < 1.5V, IOUT1 = 10mA VNOM1 1.5V, IOUT1 = 10mA VVP1 = Max(VNOM1 + 1V, 3.2V) to 5.5V IOUT1 = 10mA to 1.3A 1.4 VOUT1 20% of VNOM1 VOUT1 = 0V ISW1 = -100mA ISW1 = 100mA VVP1 = 5.5V, VSW1 = 5.5V or 0V 1.35 -2.1% -1.5% 0.1 VNOM1 VNOM1 0.15 0.0017 1.8 1.6 540 0.16 0.16 1.85 MHz kHz 0.24 0.24 1 A %VNOM1 ns 94 60 : VNOM1 refers to the nominal output voltage level for VOUT1 as defined by the Ordering Information section. Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of Philips Electronics. - 17 - www.active-semi.com Copyright (c) 2009 Active-Semi, Inc. Active-Semi ELECTRICAL CHARACTERISTICS (REG2) (VVSYS = 3.6V, TA = 25C, unless otherwise specified.) ACT8810 Rev 4, 01-Oct-09 STEP-DOWN DC/DC CONVERTERS PARAMETER VP2 Operating Voltage Range VP2 UVLO Threshold VP2 UVLO Hysteresis Quiescent Supply Current Shutdown Supply Current Output Voltage Regulation Accuracy Line Regulation Load Regulation Current Limit Oscillator Frequency PMOS On-Resistance NMOS On-Resistance SW2 Leakage Current Power Good Threshold Minimum On-Time TEST CONDITIONS Input Voltage Rising Input Voltage Falling MIN 2.9 2.7 TYP 2.8 85 130 MAX 5.5 2.9 UNIT V V mV 200 1 +2.1% +1.5% A A V %/V %/mA A REG2 Disabled, VVP2 = 4.2V VNOM2 < 1.5V, IOUT2 = 10mA VNOM2 1.5V, IOUT2 = 10mA VVP2 = Max(VNOM2 + 1V, 3.2V) to 5.5V IOUT2 = 10mA to 1.0A 1.15 VOUT2 20% of VNOM2 VOUT2 = 0V ISW2 = -100mA ISW2 = 100mA VVP2 = 5.5V, VSW2 = 5.5V or 0V 1.35 -2.1% -1.5% 0.1 VNOM2 VNOM2 0.15 0.0017 1.45 1.6 540 0.25 0.17 1.85 MHz kHz 0.38 0.26 1 A %VNOM2 ns 94 60 : VNOM2 refers to the nominal output voltage level for VOUT2 as defined by the Ordering Information section. Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of Philips Electronics. - 18 - www.active-semi.com Copyright (c) 2009 Active-Semi, Inc. Active-Semi ELECTRICAL CHARACTERISTICS (REG3) (VVSYS = 3.6V, TA = 25C, unless otherwise specified.) ACT8810 Rev 4, 01-Oct-09 STEP-DOWN DC/DC CONVERTERS PARAMETER VP3 Operating Voltage Range VP3 UVLO Threshold VP3 UVLO Hysteresis Quiescent Supply Current Shutdown Supply Current Output Voltage Regulation Accuracy Line Regulation Load Regulation Current Limit Oscillator Frequency PMOS On-Resistance NMOS On-Resistance SW3 Leakage Current Power Good Threshold Minimum On-Time TEST CONDITIONS Input Voltage Rising Input Voltage Falling MIN 2.9 2.7 TYP 2.8 85 130 MAX 5.5 2.9 UNIT V V mV 200 1 +2.1% +1.5% A A V %/V %/mA A REG3 Disabled, VVP3 = 4.2V VNOM3 < 1.5V, IOUT3 = 10mA VNOM3 1.5V, IOUT3 = 10mA VVP3 = Max(VNOM3 + 1V, 3.2V) to 5.5V IOUT3 = 10mA to 550mA 0.55 VOUT3 20% of VNOM3 VOUT3 = 0V ISW3 = -100mA ISW3 = 100mA VVP3 = 5.5V, VSW3 = 5.5V or 0V 1.35 -2.1% -1.5% 0.1 VNOM3 VNOM3 0.15 0.0017 0.7 1.6 540 0.46 0.3 1.85 MHz kHz 0.69 0.45 1 A %VNOM3 ns 94 60 : VNOM3 refers to the nominal output voltage level for VOUT3 as defined by the Ordering Information section. Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of Philips Electronics. - 19 - www.active-semi.com Copyright (c) 2009 Active-Semi, Inc. Active-Semi TYPICAL PERFORMANCE CHARACTERISTICS ACT8810 Rev 4, 01-Oct-09 STEP-DOWN DC/DC CONVERTERS (ACT8810QJ343, VVP1 = VVP2 = 3.6V, L = 3.3H, CVP1 = CVP2 = 4.7F, COUT1 = 22F, COUT2 = 10F, TA = 25C, unless otherwise specified.) REG1 Efficiency vs. Load Current 100 ACT8810-003 VVSYS = 3.6V VVSYS = 5.2V VVSYS = 4.6V 60 VVSYS = 4.2V 100 80 REG2 Efficiency vs. Load Current ACT8810-004 REG1 Efficiency (%) REG2 Efficiency (%) 80 VVSYS = 3.6V VVSYS = 5.2V 60 VVSYS = 4.2V 40 VVSYS = 4.6V 40 20 VOUT1 = 3.3V 0 2 20 200 2000 20 VOUT2 = 1.2V 0 1 10 100 1000 Load Current (mA) Load Current (mA) OUT1 Regulation Voltage vs. Temperature 3.318 OUT2 Regulation Voltage vs. Temperature 1.212 ACT8810-005 ACT8810-006 OUT2 Regulation Voltage (V) 3.312 3.309 3.306 3.303 3.300 3.297 3.294 3.291 3.288 3.285 3.282 -40 -20 0 20 40 60 OUT3 Regulation Voltage (V) 3.315 IOUT1 = 35mA IOUT2 = 35mA 1.208 1.204 1.200 1.196 1.192 1.188 85 -40 -20 0 20 40 60 85 Temperature (C) Temperature (C) REG1 RDSON vs. VP1 Input Voltage 0.18 0.16 PMOS 0.5 ACT8810-007 REG2 RDSON vs. VP2 Input Voltage ACT8810-008 REG1 RDSON (m) 0.12 0.10 0.08 0.06 0.04 0.02 0 3.5 4.0 4.5 5.0 NMOS REG2 RDSON (m) 0.14 0.4 0.3 PMOS 0.2 NMOS 0.1 0 5.5 6.0 6.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VP1 Input Voltage (V) VP2 Input Voltage (V) Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of Philips Electronics. - 20 - www.active-semi.com Copyright (c) 2009 Active-Semi, Inc. Active-Semi TYPICAL PERFORMANCE CHARACTERISTICS CONT'D (ACT8810QJ343, VVP3 = 3.6V, L = 3.3H, CVP3 = 4.7F, COUT3 = 10F, TA = 25C, unless otherwise specified.) ACT8810 Rev 4, 01-Oct-09 STEP-DOWN DC/DC CONVERTERS REG3 Efficiency vs. Load Current 100 ACT8810-009 VOUT3 = 1.2V VVSYS = 3.6V 80 VVSYS = 4.6V VVSYS = 4.2V REG3 Efficiency (%) 60 40 20 0 1 10 100 1000 Load Current (mA) OUT3 Regulation Voltage vs. Tempera1.812 ACT8810-010 OUT1 Regulation Voltage (V) IOUT3 = 35mA 1.808 1.804 1.800 1.796 1.792 1.788 -40 -20 0 20 40 60 85 Temperature (C) REG3 RDSON vs. VP3 Input Voltage 0.50 0.45 ACT8810-011 REG3 RDSON (m) 0.40 0.35 0.30 0.25 0.20 0.15 0.1 3.0 3.5 4.0 4.5 5.0 PMOS NMOS 5.5 6.0 VP3 Input Voltage (V) Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of Philips Electronics. - 21 - www.active-semi.com Copyright (c) 2009 Active-Semi, Inc. Active-Semi REGISTER DESCRIPTIONS Note: See Table 1 for default register settings. ACT8810 Rev 4, 01-Oct-09 STEP-DOWN DC/DC CONVERTERS Table 4: REG1 Control Register Map ADDRESS 10h 11h 12h 13h DATA D7 R R R R D6 R R R VRANGE D5 R R D4 R R D3 VSET1 R R D2 R nFLTMSK VSET0 D1 R OK D0 R ON R: Read-Only bits. Default Values May Vary. Table 5: REG1 Control Register Bit Descriptions ADDRESS 10h 10h 11h 12h ON NAME VSET1 BIT [5:0] [7:6] [7:0] [0] ACCESS R/W R R R/W FUNCTION REG1 Standby Output Voltage Selection DESCRIPTION See Table 4 READ ONLY READ ONLY REG1 Enable 0 1 0 1 0 1 REG1 Disable REG1 Enable Output is not OK Output is OK Masked Not Mask READ ONLY 12h OK [1] R REG1 Power-OK 12h 12h 13h 13h 13h nFLTMSK [2] [7:3] R/W R R/W R/W R REG1 Output Voltage Fault Mask Option VSET0 VRANGE [5:0] [6] [7] REG1 Output Voltage Selection REG1 Voltage Range 0 1 See Table 4 Min VOUT = 0.8V Min VOUT = 1.25V READ ONLY Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of Philips Electronics. - 22 - www.active-semi.com Copyright (c) 2009 Active-Semi, Inc. Active-Semi REGISTER DESCRIPTIONS CONT'D Table 6: REG1/VSETx[ ] Output Voltage Setting REG1/VSETx[5:4] REG1/VSETx[3:0] 00 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Adjustable 0.800 0.800 0.800 0.800 0.800 0.800 0.800 0.825 0.850 0.875 0.900 0.925 0.950 0.975 1.000 ACT8810 Rev 4, 01-Oct-09 STEP-DOWN DC/DC CONVERTERS REG1/VRANGE[ ] = [0] 01 1.025 1.050 1.075 1.100 1.125 1.150 1.175 1.200 1.225 1.250 1.275 1.300 1.325 1.350 1.375 1.400 REG1/VRANGE[ ] = [1] 11 1.825 1.850 1.875 1.900 1.925 1.950 1.975 2.000 2.025 2.050 2.075 2.100 2.125 2.150 2.175 2.200 10 1.425 1.450 1.480 1.500 1.525 1.550 1.575 1.600 1.625 1.650 1.675 1.700 1.725 1.750 1.775 1.800 00 Adjustable 1.300 1.350 1.400 1.450 1.500 1.550 1.600 1.650 1.700 1.750 1.800 1.850 1.900 1.950 2.000 01 2.050 2.100 2.150 2.200 2.250 2.300 2.350 2.400 2.450 2.500 2.550 2.600 2.650 2.700 2.750 2.800 10 2.850 2.900 2.950 3.000 3.050 3.100 3.150 3.200 3.250 3.300 3.350 3.400 3.450 3.500 3.550 3.600 11 3.650 3.700 3.750 3.800 3.850 3.900 3.950 4.000 4.050 4.100 4.150 4.200 4.250 4.300 4.350 4.400 : Care must be taken when adjusting the VRANGE[ ] selection at address 13h bit-6 to avoid undesired output voltage selections. The VRANGE bit allows selection of the two output voltage ranges available for REG1, REG2 and REG3 (VRANGE = 0 - VOUT range 0.8V to 2.2V, VRANGE = 1 - VOUT range 1.3V to 4.4V). It is recommended that the user first establishes if the new VOUT voltage is within the current selected voltage range (selected by VRANGE) prior to changing the value of the VRANGE bit. : Refer to the Output Voltage Programming section for more information. Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of Philips Electronics. - 23 - www.active-semi.com Copyright (c) 2009 Active-Semi, Inc. Active-Semi REGISTER DESCRIPTIONS Note: See Table 1 for default register settings. ACT8810 Rev 4, 01-Oct-09 Table 7: REG2 Control Register Map ADDRESS 20h 21h 22h 23h DATA D7 R R R R D6 R R R VRANGE D5 R R D4 R R D3 VSET1 R R D2 R nFLTMSK VSET0 D1 R OK D0 R ON R: Read-Only bits. Default Values May Vary. Table 8: REG2 Control Register Bit Descriptions ADDRESS 20h 20h 21h 22h ON NAME VSET1 BIT [5:0] [7:6] [7:0] [0] ACCESS R/W R R R/W FUNCTION REG2 Standby Output Voltage Selection DESCRIPTION See Table 7 READ ONLY READ ONLY REG2 Enable 0 1 0 1 0 1 REG2 Disable REG2 Enable Output is not OK Output is OK Masked Not Mask READ ONLY 22h OK [1] R REG2 Power-OK 22h 22h 23h 23h 23h nFLTMSK [2] [7:3] R/W R R/W R/W R REG2 Output Voltage Fault Mask Option VSET0 VRANGE [5:0] [6] [7] REG2 Output Voltage Selection REG2 Voltage Range 0 1 See Table 7 Min VOUT = 0.8V Min VOUT = 1.25V READ ONLY Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of Philips Electronics. - 24 - www.active-semi.com Copyright (c) 2009 Active-Semi, Inc. Active-Semi REGISTER DESCRIPTIONS CONT'D Table 9: REG2/VSETx[ ] Output Voltage Setting REG2/VSETx[5:4] REG2/VSETx[3:0] 00 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Adjustable 0.800 0.800 0.800 0.800 0.800 0.800 0.800 0.825 0.850 0.875 0.900 0.925 0.950 0.975 1.000 ACT8810 Rev 4, 01-Oct-09 STEP-DOWN DC/DC CONVERTERS REG2/VRANGE[ ] = [0] 01 1.025 1.050 1.075 1.100 1.125 1.150 1.175 1.200 1.225 1.250 1.275 1.300 1.325 1.350 1.375 1.400 REG2/VRANGE[ ] = [1] 11 1.825 1.850 1.875 1.900 1.925 1.950 1.975 2.000 2.025 2.050 2.075 2.100 2.125 2.150 2.175 2.200 10 1.425 1.450 1.480 1.500 1.525 1.550 1.575 1.600 1.625 1.650 1.675 1.700 1.725 1.750 1.775 1.800 00 Adjustable 1.300 1.350 1.400 1.450 1.500 1.550 1.600 1.650 1.700 1.750 1.800 1.850 1.900 1.950 2.000 01 2.050 2.100 2.150 2.200 2.250 2.300 2.350 2.400 2.450 2.500 2.550 2.600 2.650 2.700 2.750 2.800 10 2.850 2.900 2.950 3.000 3.050 3.100 3.150 3.200 3.250 3.300 3.350 3.400 3.450 3.500 3.550 3.600 11 3.650 3.700 3.750 3.800 3.850 3.900 3.950 4.000 4.050 4.100 4.150 4.200 4.250 4.300 4.350 4.400 : Care must be taken when adjusting the VRANGE[ ] selection at address 23h bit-6 to avoid undesired output voltage selections. The VRANGE bit allows selection of the two output voltage ranges available for REG1, REG2 and REG3 (VRANGE = 0 - VOUT range 0.8V to 2.2V, VRANGE = 1 - VOUT range 1.3V to 4.4V). It is recommended that the user first establishes if the new VOUT voltage is within the current selected voltage range (selected by VRANGE) prior to changing the value of the VRANGE bit. : Refer to the Output Voltage Programming section for more information. Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of Philips Electronics. - 25 - www.active-semi.com Copyright (c) 2009 Active-Semi, Inc. Active-Semi REGISTER DESCRIPTIONS Note: See Table 1 for default register settings. ACT8810 Rev 4, 01-Oct-09 STEP-DOWN DC/DC CONVERTERS Table 10: REG3 Control Register Map ADDRESS 30h 31h 32h 33h DATA D7 R R R R D6 R R R VRANGE D5 R R D4 R R D3 VSET1 R R D2 R nFLTMSK VSET0 D1 R OK D0 R ON R: Read-Only bits. Default Values May Vary. W/E: Write-Exact bits. Read/Write bits which must be written exactly as specified in Table 1 Table 11: REG3 Control Register Bit Descriptions ADDRESS 30h 30h 31h 32h ON NAME VSET1 BIT [5:0] [7:6] [7:0] [0] ACCESS R/W R R R/W FUNCTION REG3 Standby Output Voltage Selection DESCRIPTION See Table 10 READ ONLY READ ONLY REG3 Enable 0 1 0 1 0 1 REG3 Disable REG3 Enable Output is not OK Output is OK Masked Not Mask READ ONLY 32h OK [1] R REG3 Power-OK 32h 32h 33h 33h 33h nFLTMSK [2] [7:3] R/W R R/W R/W R REG3 Output Voltage Fault Mask Option VSET0 VRANGE [5:0] [6] [7] REG3 Output Voltage Selection REG3 Voltage Range 0 1 See Table 10 Min VOUT = 0.8V Min VOUT = 1.25V READ ONLY Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of Philips Electronics. - 26 - www.active-semi.com Copyright (c) 2009 Active-Semi, Inc. Active-Semi ACT8810 Rev 4, 01-Oct-09 STEP-DOWN DC/DC CONVERTERS REGISTER DESCRIPTIONS CONT'D Table 12: REG3/VSETx[ ] Output Voltage Setting REG3/VSETx[5:4] REG3/VSETx[3:0] 00 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Adjustable 0.800 0.800 0.800 0.800 0.800 0.800 0.800 0.825 0.850 0.875 0.900 0.925 0.950 0.975 1.000 REG3/VRANGE[ ] = [0] 01 1.025 1.050 1.075 1.100 1.125 1.150 1.175 1.200 1.225 1.250 1.275 1.300 1.325 1.350 1.375 1.400 REG3/VRANGE[ ] = [1] 11 1.825 1.850 1.875 1.900 1.925 1.950 1.975 2.000 2.025 2.050 2.075 2.100 2.125 2.150 2.175 2.200 10 1.425 1.450 1.480 1.500 1.525 1.550 1.575 1.600 1.625 1.650 1.675 1.700 1.725 1.750 1.775 1.800 00 Adjustable 1.300 1.350 1.400 1.450 1.500 1.550 1.600 1.650 1.700 1.750 1.800 1.850 1.900 1.950 2.000 01 2.050 2.100 2.150 2.200 2.250 2.300 2.350 2.400 2.450 2.500 2.550 2.600 2.650 2.700 2.750 2.800 10 2.850 2.900 2.950 3.000 3.050 3.100 3.150 3.200 3.250 3.300 3.350 3.400 3.450 3.500 3.550 3.600 11 3.650 3.700 3.750 3.800 3.850 3.900 3.950 4.000 4.050 4.100 4.150 4.200 4.250 4.300 4.350 4.400 : Care must be taken when adjusting the VRANGE[ ] selection at address 33h bit-6 to avoid undesired output voltage selections. The VRANGE bit allows selection of the two output voltage ranges available for REG1, REG2 and REG3 (VRANGE = 0 - VOUT range 0.8V to 2.2V, VRANGE = 1 - VOUT range 1.3V to 4.4V). It is recommended that the user first establishes if the new VOUT voltage is within the current selected voltage range (selected by VRANGE) prior to changing the value of the VRANGE bit. : Refer to the Output Voltage Programming section for more information. Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of Philips Electronics. - 27 - www.active-semi.com Copyright (c) 2009 Active-Semi, Inc. Active-Semi FUNCTIONAL DESCRIPTION General Description REG1, REG2, and REG3 are fixed-frequency, current-mode, synchronous PWM step-down converters that are capable of supplying up to 1.3A, 1.0A, and 0.55A of output current, respectively. These regulators operate with a fixed frequency of 1.6MHz, minimizing noise in sensitive applications and allowing the use of small external components, and achieve peak efficiencies of up to 97%. Each step-down DC/DC is available with a variety of standard and custom output voltages, which may be software-controlled by systems requiring advanced power management functions, via the I2C interface. ACT8810 Rev 4, 01-Oct-09 STEP-DOWN DC/DC CONVERTERS 1) ONx is asserted high to enable REGx, 2) REGx/ONx[ ] is set to 1 when ONx is high In addition REG1, REG2, or REG3 may be enabled when nPBIN is pushed low via 100k resistance. It depends on sequence is set. See the Control Sequence section for more information. When none of these conditions are true, REG1, REG2 and REG3 are disabled, and each regulator's quiescent supply current drops to less than 1A. Power-OK REG1, REG2 and REG3 each feature a variety of status bits that can be read by the system microprocessor. If any output falls below its powerOK threshold, typically 6% below the programmed regulation voltage, REGx/OK[ ] is cleared to 0. Buck Regulator PFM/PWM Operating Modes The buck converters offer PFM/PWM operating modes to maximize efficiency under both light and full load conditions. The device will automatically transition from fixed frequency PWM mode to PFM mode when the output current is approximately 100mA. In PFM mode, the device maintains output voltage regulation by adjusting the switching frequency. The device transitions into fixed frequency PWM mode when the output current reaches approximately 100mA. Soft-Start REG1, REG2 and REG3 each include matched soft-start circuitry. When enabled, the output voltages track the internal 80s soft-start ramp and both power up in a monotonic manner that is independent of loading on either output. This circuitry ensures that each output powers up in a controlled manner, greatly simplifying power sequencing design considerations. 100% Duty Cycle Operation REG1, REG2 and REG3 are each capable of operating at up to 100% duty cycle. During 100% duty-cycle operation, the high-side power MOSFET is held on continuously, providing a direct connection from the input to the output (through the inductor), ensuring the lowest possible dropout voltage in battery powered applications. Compensation REG1, REG2 and REG3 utilize current-mode control and a proprietary internal compensation scheme to simultaneously simplify external component selection and optimize transient performance over their full operating range. No compensation design is required; simply follow a few simple guide lines described below when choosing external components. Synchronous Rectification REG1, REG2 and REG3 each feature integrated channel synchronous rectifiers, maximizing efficiency and minimizing the total solution size and cost by eliminating the need for external rectifiers. Input Capacitor Selection The input capacitor reduces peak currents and noise induced upon the voltage source. A 4.7F ceramic capacitor for each of REG1, REG2 and REG3 is recommended for most applications. Enabling and Disabling REG1, REG2 and REG3 REG1, REG2, and REG3 are typically enabled and disabled using the ACT8810's closed-loop enable/disable control scheme, including the nPBIN input. Refer to the System Startup and Shutdown section for more information about this function. Each regulator is enabled when the following conditions are met: Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of Philips Electronics. Output Capacitor Selection For most applications, 22F ceramic output capacitors are recommended for REG1 and 10F ceramic output capacitors are recommended for REG2, REG3. Although the these regulators were designed to take advantage of the benefits of ceramic capacitors, namely small size and very-low ESR, low-ESR tantalum capacitors can provide acceptable results as well. - 28 www.active-semi.com Copyright (c) 2009 Active-Semi, Inc. Active-Semi FUNCTIONAL DESCRIPTION CONT'D Inductor Selection REG1, REG2 and REG3 utilize current-mode control and a proprietary internal compensation scheme to simultaneously simplify external component selection and optimize transient performance over their full operating range. REG1, REG2 and REG3 of the device were optimized for operation with and 3.3H inductor, although inductors in the 2.2H to 4.7H range can be used. Choose an inductor with a low DC-resistance, and avoid inductor saturation by choosing inductors with DC ratings that exceed the maximum output current of the application by at least 30%. Figure 8: Output Voltage Programming OUTx ACT8810 FBx CFF ACT8810 Rev 4, 01-Oct-09 STEP-DOWN DC/DC CONVERTERS RFB1 RFB2 Finally choose CFF using the following equation: C FF = 2.2 x 10 -6 R FB1 (2) Output Voltage Programming By default, REG1, REG2 and REG3 each power up and regulate to their default output voltage, as defined in the Ordering Information section. Once the system is enabled, each regulator's output voltage may be modified through either the I2C interface or the Voltage Selection (VSEL) pin. Programming via the I2C Interface Following startup, REG1, REG2, and REG3 may be independently programmed to different values by writing to the REGx/VSETx[_] and REGx/VRANGE[_] registers via the I2C interface. To program each regulator, first select the desired output voltage range via the REGx/VRANGE[ ] bit. Each regulator supports two overlapping ranges; set REGx/VRANGE[_] to 0 for voltages below 2.245V, set REGx/VRANGE[_] to 1 for voltages above 1.25V. Once the desired range has been selected, program the output to a voltage within that range by setting the REGx/VSETx bits. For more information about the output voltage setting options, refer to Tables 4, 7, and 10, for REG1, REG2, and REG3, respectively. Programming with Adjustable Option Figure 8 shows the feedback network necessary to set the output voltage when using the adjustable output voltage option. Select components as follows: Set RFB2 = 51k, then calculate RFB1 using the following equation: Where RFB1 = 47k, use 47pF. When using Adjustable Option, OUTx pins works as FBx function. Output Voltage Selection Pin (VSEL) ACT8810's VSEL pin provides a simple means of alternating between two preset output voltage settings, such as may be needed for dynamic voltage selection (DVS). The operation of this pin is as follows: when VSEL is driven to GA or a logic low, the output voltages of REG1, REG2, and REG3 are each defined by their VSET0[ ] register. when VSEL is driven to VSYS or a logic high, the output voltages of REG1, REG2, and REG3 are each defined by their VSET1[ ] register. By default, each regulator's VSET0[ ] and VSET1[ ] registers are both programmed to the same voltage, as defined in the Ordering Information section. As a result, toggling VSET under default conditions has no affect. However, by re-programming one or more regulator's VSET0[ ] and/or VSET1[ ] registers, one can easily toggle these regulators' output voltages between two sets of voltages, such as to implement 'normal' and 'standby' modes in a system utilizing the ACT8810 to implement an advanced power management architecture. PCB Layout Considerations High switching frequencies and large peak currents make PC board layout an important part of stepdown DC/DC converter design. A good design minimizes excessive EMI on the feedback paths and voltage gradients in the ground plane, both of which can result in instability or regulation errors. Step-down DC/DCs exhibit discontinuous input current, so the input capacitors should be placed as - 29 www.active-semi.com Copyright (c) 2009 Active-Semi, Inc. V R FB 1 = R FB 2 OUTx - 1 V FBx (1) Where VFBx is 0.625V when REGx x VRANGE[ ] = 0 and 1.25V when REGx x VRANGE[ ] = 1 Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of Philips Electronics. Active-Semi FUNCTIONAL DESCRIPTION CONT'D close as possible to the IC, and avoiding the use of vias if possible. The inductor, input filter capacitor, and output filter capacitor should be connected as close together as possible, with short, direct, and wide traces. The ground nodes for each regulator's power loop should be connected at a single point in a starground configuration, and this point should be connected to the backside ground plane with multiple vias. The output node for each regulator should be connected to its corresponding OUTx pin through the shortest possible route, while keeping sufficient distance from switching nodes to prevent noise injection. Finally, the exposed pad should be directly connected to the backside ground plane using multiple vias to achieve low electrical and thermal resistance. ACT8810 Rev 4, 01-Oct-09 STEP-DOWN DC/DC CONVERTERS Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of Philips Electronics. - 30 - www.active-semi.com Copyright (c) 2009 Active-Semi, Inc. Active-Semi ELECTRICAL CHARACTERISTICS (REG4) (VINL = 3.6V, COUT4 = 1F, TA = 25C, unless otherwise specified.) ACT8810 Rev 4, 01-Oct-09 LOW-DROPOUT LINEAR REGULATORS PARAMETER INL Operating Voltage Range INL UVLO Threshold UVLO Hysteresis Output Voltage Accuracy Line Regulation Error Load Regulation Error Power Supply Rejection Ratio TEST CONDITIONS VINL Input Rising VINL Input Falling TA = 25C TA = -40C to 85C VINL = Max(VOUT5 + 0.5V, 3.6V) to 5.5V IOUT5 = 1mA to 360mA f = 1kHz, IOUT4 = 360mA, COUT4 = 1F f = 10kHz, IOUT4 = 360mA, COUT4 = 1F Regulator Enabled Regulator Disabled IOUT4 = 160mA, VOUT4 > 3.1V MIN 2.6 2.4 TYP 2.5 0.1 MAX 5.5 2.6 UNIT V V V -2% -3% VNOM4 VNOM4 0 -0.006 70 60 35 0 100 +2% +3% V %/V %/mA dB Supply Current per Output Dropout Voltage3 Output Current Current Limit Internal Soft-Start A 200 360 mV mA s % VRMS 20 F VOUT4 = 95% of regulation voltage 400 100 88 40 1 Power Good Flag High Threshold VOUT4, hysteresis = -2% Output Noise Stable COUT4 Range Discharge Resistor in Shutdown LDO Disabled, DIS4[ ] = [1] COUT4 = 10F, f = 10Hz to 100kHz 1000 : VNOM4 refers to the nominal output voltage level for VOUT4 as defined by the Ordering Information section. : PSRR is lower with VSET < 1.25V 3: Dropout Voltage is defined as the differential voltage between input and output when the output voltage drops 100mV below the regulation voltage at 1V differential voltage (for 2.8V output voltage or higher) : LDO current limit is defined as the output current at which the output voltage drops to 95% of the respective regulation voltage. Under heavy overload conditions the output current limit folds back by 40% (typ) Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of Philips Electronics. - 31 - www.active-semi.com Copyright (c) 2009 Active-Semi, Inc. Active-Semi ELECTRICAL CHARACTERISTICS (REG5) (VINL = 3.6V, COUT5 = 1F, TA = 25C, unless otherwise specified.) ACT8810 Rev 4, 01-Oct-09 LOW-DROPOUT LINEAR REGULATORS PARAMETER INL Operating Voltage Range INL UVLO Threshold UVLO Hysteresis Output Voltage Accuracy Line Regulation Error Load Regulation Error Power Supply Rejection Ratio TEST CONDITIONS VINL Input Rising VINL Input Falling TA = 25C TA = -40C to 85C VINL = Max(VOUT5 + 0.5V, 3.6V) to 5.5V IOUT5 = 1mA to 360mA f = 1kHz, IOUT5 = 360mA, COUT5 = 1F f = 10kHz, IOUT5 = 360mA, COUT5 = 1F Regulator Enabled Regulator Disabled IOUT5 = 160mA, VOUT5 > 3.1V MIN 2.6 2.4 TYP 2.5 0.1 MAX 5.5 2.6 UNIT V V V -2% -3% VNOM5 VNOM5 0 -0.006 70 60 35 0 100 +2% +3% V %/V %/mA dB Supply Current per Output Dropout Voltage3 Output Current Current Limit Internal Soft-Start Output Noise Stable COUT5 Range Discharge Resistor in Shutdown A 200 360 mV mA mA VOUT5 = 95% of regulation voltage 400 100 s VRMS 20 F COUT5 = 10F, f = 10Hz to 100kHz 1 LDO Disabled, DIS5[ ] = [1] 40 1000 : VNOM5 refers to the nominal output voltage level for VOUT5 as defined by the Ordering Information section. : PSRR is lower with VSET < 1.25V 3: Dropout Voltage is defined as the differential voltage between input and output when the output voltage drops 100mV below the regulation voltage at 1V differential voltage (for 2.8V output voltage or higher) : LDO current limit is defined as the output current at which the output voltage drops to 95% of the respective regulation voltage. Under heavy overload conditions the output current limit folds back by 40% (typ) Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of Philips Electronics. - 32 - www.active-semi.com Copyright (c) 2009 Active-Semi, Inc. Active-Semi TYPICAL PERFORMANCE CHARACTERISTICS (ACT8810QJ343, VVSYS = 5V, TA = 25C, unless otherwise specified.) ACT8810 Rev 4, 01-Oct-09 LOW-DROPOUT LINEAR REGULATORS Output Regulation Voltage vs. Load Current Output Regulation Voltage (%) 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 0 40 80 120 160 200 240 280 320 360 225 200 ACT8810-012 Dropout Voltage vs. Output Current ACT8810-013 Dropout Voltage (mV) 175 150 125 100 75 50 25 0 0 50 100 150 200 250 300 3.1V 3.3V 3.6V REG4, REG5 360 Load Current (mA) Output Current (mA) Output Voltage Deviation vs. Temperature Output Voltage Deviation (%) 2.00 1.50 ACT8810-014 ILOAD = 0mA LDO Output Voltage Noise ACT8810-015 1.00 0.50 CH1 0.00 -0.5 -40 -15 10 35 60 85 CH1: VOUTx, 200V/div (AC COUPLED) TIME: 200ms/div CREF = 10nF Temperature (C) Region of Stable COUT ESR vs. Output Current ACT8810-016 1 ESR () 0.1 Stable ESR 0.01 0 50 100 150 200 250 300 360 Output Current (mA) Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of Philips Electronics. - 33 - www.active-semi.com Copyright (c) 2009 Active-Semi, Inc. Active-Semi REGISTER DESCRIPTIONS Note: See Table 1 for default register settings. ACT8810 Rev 4, 01-Oct-09 LOW-DROPOUT LINEAR REGULATORS Table 13: REG45 Control Register Map ADDRESS 40h 41h 43h DATA D7 DIS4 DIS5 R D6 R R R D5 ON4 ON5 R D4 D3 D2 VSET4 VSET5 D1 D0 R R R nFLTMSK OK R: Read-Only bits. Default Values May Vary. Table 14: REG45 Control Register Bit Descriptions ADDRESS 40h 40h 40h 40h 41h 41h 41h 41h DIS5 DIS4 VSET5 ON5 NAME VSET4 ON4 BIT [4:0] [5] [6] [7] [4:0] [5] [6] [7] ACCESS R/W R/W R R/W R/W R/W R R/W FUNCTION REG4 Output Voltage Selection REG4 Enable 0 1 DESCRIPTION See Table 15 REG4 Disable REG4 Enable READ ONLY REG4 Discharge Enable REG5 Output Voltage Selection REG5 Enable 0 1 Discharge Disable Discharge Enable See Table 15 0 1 REG5 Disable REG5 Enable READ ONLY REG5 Discharge Enable 0 1 0 1 0 1 Discharge Disable Discharge Enable Output is not OK Output is OK Masked Not Mask READ ONLY 43h OK [0] R REG4 Power-OK REG4 Output Voltage Fault Mask Option 43h 43h nFLTMSK [1] [7:2] R/W R Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of Philips Electronics. - 34 - www.active-semi.com Copyright (c) 2009 Active-Semi, Inc. Active-Semi REGISTER DESCRIPTIONS CONT'D Table 15: REG45/VSETx[ ] Output Voltage Setting REG45CFG/VSETx[2:0] 000 001 010 011 100 101 110 111 ACT8810 Rev 4, 01-Oct-09 LOW-DROPOUT LINEAR REGULATORS REG45CFG/VSETx[4:3] 00 0.90 1.00 1.10 1.20 1.25 1.30 1.35 1.40 01 1.45 1.50 1.55 1.60 1.70 1.75 1.80 1.85 10 1.90 2.00 2.10 2.20 2.40 2.50 2.60 2.70 11 2.75 2.80 2.85 2.90 3.00 3.10 3.20 3.30 Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of Philips Electronics. - 35 - www.active-semi.com Copyright (c) 2009 Active-Semi, Inc. Active-Semi FUNCTIONAL DESCRIPTION General Description REG4 and REG5 are low-noise, low-dropout linear regulators (LDOs) that are optimized for low noise and high-PSRR operation, achieving more than 60dB PSRR at frequencies up to 10kHz. ACT8810 Rev 4, 01-Oct-09 LOW-DROPOUT LINEAR REGULATORS which filters noise from the reference, providing a low noise voltage reference to the LDOs. Bypass REFBP to GA with a 0.01F ceramic capacitor. Optional LDO Output Discharge Each of the ACT8810's LDOs features an optional, independent output voltage discharge feature. When this feature is enabled, the LDO output is discharged to ground through a 1k resistance when the LDO is shutdown. This feature may be enabled or disabled via the I2C interface by writing to the REG45CFG/DISx[ ] bits. LDO Output Voltage Programming All LDOs feature independently-programmable output voltages that are set via the I2C serial interface, increasing the ACT8810's flexibility while reducing total solution size and cost. Set the output voltage by writing to the REG45CFG/VSETx[ ] registers. Output Capacitor Selection REG4 and REG5 each require only a small ceramic capacitor for stability. For best performance, each output capacitor should be connected directly between the OUTx and GA pins as possible, with a short and direct connection. To ensure best performance for the device, the output capacitor should have a minimum capacitance of 1F, and ESR value between 10m and 200m. High quality ceramic capacitors such as X7R and X5R dielectric types are strongly recommended. Output Current Capability REG4 and REG5 each supply an output current of 360mA. Excellent performance is achieved over this load current range. Output Current Limit In order to ensure safe operation under over-load conditions, each LDO features current-limit circuitry with current fold-back. The current-limit circuitry limits the current that can be drawn from the output, providing protection in over-load conditions. For additional protection under extreme over current conditions, current-fold-back protection reduces the current-limit by approximately 40% under extreme overload conditions. PCB Layout Considerations The ACT8810's LDOs provide good DC, AC, and noise performance over a wide range of operating conditions, and are relatively insensitive to layout considerations. When designing a PCB, however, careful layout is necessary to prevent other circuitry from degrading LDO performance. A good design places input and output capacitors as close to the LDO inputs and output as possible, and utilizes a star-ground configuration for all regulators to prevent noise-coupling through ground. Output traces should be routed to avoid close proximity to noisy nodes, particularly the SW nodes of the DC/DCs. REFBP is a filtered reference noise, and internally has a direct connection to the linear regulator controller. Any noise injected onto REFBP will directly affect the outputs of the linear regulators, and therefore special care should be taken to ensure that no noise is injected to the outputs via REFBP. As with the LDO output capacitors, the REFBP bypass capacitor should be placed as close to the IC as possible, with short, direct connections to the star-ground. Avoid the use of vias whenever possible. Noisy nodes, such as from the DC/DCs, should be routed as far away from REFBP as possible. - 36 www.active-semi.com Copyright (c) 2009 Active-Semi, Inc. Enabling and Disabling the LDOs All LDOs feature independent enable/disable control via the I2C serial interface. Independently enable or disable each output by writing to the appropriate REG45CFG/ONx[ ] bit. In addition REG4 or REG5 may be enable when nPBIN is pushed low via 100k resistance. It depends on sequence is set. See the Control Sequence section for more information. Power-OK REG4 features power-OK status bit that can be read by the system microprocessor via the I2C interface. If an output voltage is lower than the power-OK threshold, typically 12% below the programmed regulation voltage, the corresponding REG45CFG/OK[ ] will clear to 0. Reference Bypass Pin The ACT8810 contains a reference bypass pin Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of Philips Electronics. Active-Semi ELECTRICAL CHARACTERISTICS (REG6) (TA = 25C, unless otherwise specified.) ACT8810 Rev 4, 01-Oct-09 RTC LOW-DROPOUT LINEAR REGULATOR PARAMETER Input Supply Range Output Voltage Accuracy Line Regulation Error Load Regulation Error Input Supply Current Dropout Voltage Output Current Current Limit3 Stable COUT6 Range TA = 25C TEST CONDITIONS MIN 2.6 -2% -3% TYP VNOM6 VNOM6 0.1 -0.01 6 35 MAX 5.5 +2% +3% UNIT V V %/V %/mA TA = -40C to 85C VINL = VOUT6 + 0.5V to VINL = 5.5V IOUT6 = 0mA to 30mA ON1 = ON2 = ON3 = GA IOUT6 = 10mA 12 70 30 A mV mA mA VOUT6 = 95% of regulation voltage 45 1 20 F : VNOM6 refers to the nominal output voltage level for VOUT6 as defined by the Ordering Information section. : Dropout Voltage is defined as the differential voltage between input and output when the output voltage drops 100mV below the regulation voltage at 1V differential voltage (for 2.8V output voltage or higher) 3: LDO current limit is defined as the output current at which the output voltage drops to 95% of the respective regulation voltage. Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of Philips Electronics. - 37 - www.active-semi.com Copyright (c) 2009 Active-Semi, Inc. Active-Semi REGISTER DESCRIPTIONS Note: See Table 1 for default register settings. ACT8810 Rev 4, 01-Oct-09 RTC LOW-DROPOUT LINEAR REGULATOR Table 16: REG6 Control Register Map ADDRESS 42h DATA D7 R D6 R D5 R D4 D3 D2 VSET6 D1 D0 R: Read-Only bits. Default Values May Vary. Table 17: REG6 Control Register Bit Descriptions ADDRESS 42h 42h NAME VSET6 BIT [4:0] [7:5] ACCESS R/W R FUNCTION REG6 Output Voltage Selection DESCRIPTION See Table 18 READ ONLY Table 18: REG6/VSETx[ ] Output Voltage Setting REG6CFG/VSETx[2:0] 000 001 010 011 100 101 110 111 REG6CFG/VSETx[4:3] 00 0.90 1.00 1.10 1.20 1.25 1.30 1.35 1.40 01 1.45 1.50 1.55 1.60 1.70 1.75 1.80 1.85 10 1.90 2.00 2.10 2.20 2.40 2.50 2.60 2.70 11 2.75 2.80 2.85 2.90 3.00 3.10 3.20 3.30 Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of Philips Electronics. - 38 - www.active-semi.com Copyright (c) 2009 Active-Semi, Inc. Active-Semi FUNCTIONAL DESCRIPTION General Description REG6 is an always-on, low-dropout linear regulator (LDO) that is optimized for RTC and backup-battery applications. REG6 features low-quiescent supply current, current-limit protection, and reverse-current protection, and is ideally suited for always-on power supply applications, such as for a real-time clock, or as a backup-battery or super-cap charger. ACT8810 Rev 4, 01-Oct-09 RTC LOW-DROPOUT LINEAR REGULATOR Backup Battery Charging REG6 features a constant current-limit, which protects the IC under output short-circuit conditions as well as provides a constant charge current, when operating as a backup battery charger. As shown in Figure 10, REG6 features a CC/CV output characteristic, regulating its output voltage for load currents up to 30mA, and regulating output current when the load exceeds (typically) 60mA. Figure 10: REG6 Output Voltage REG6 Output Voltage vs. Load Current 4 ACT8810-017 Output Voltage By default, REG6's output voltage is as defined in the Ordering Information section. However, this voltage may be programmed by writing to the REG6CFG/VSETx[ ] register via the I2C interface. Reverse-Current Protection REG6 features internal circuitry that limits the reverse supply current to less than 1A when the input voltage falls below the output voltage, as can be encountered in backup-battery charging applications. REG6's internal circuitry monitors the input and the output, and disconnects internal circuitry and parasitic diodes when the input voltage falls below the output voltage, greatly minimizing backup battery discharge. Output Voltage (V) 3 2 Constant Voltage Region Constant Current Region 1 0 Typical Application Voltage Regulators REG6 is ideally suited for always-on voltageregulation applications, such as for real-time clock and memory keep-alive applications. This regulator requires only a small ceramic capacitor with a minimum capacitance of 1F for stability. For best performance, the output capacitor should be connected directly between the output and GA, with a short and direct connection. Figure 9: Typical Application of RTC LDO 0 20 40 60 80 100 Load Current (mA) ACT8810 OUT6 RTC Supper cap or Back-up battery Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of Philips Electronics. - 39 - www.active-semi.com Copyright (c) 2009 Active-Semi, Inc. Active-Semi ActivePath ELECTRICAL CHARACTERISTICS (VCHG_IN = 5V, TA = 25C, unless otherwise specified.) ACT8810 Rev 4, 01-Oct-09 TM CHARGER PARAMETER ActivePath CHG_IN Operating Voltage Range CHG_IN UVLO Threshold CHG_IN UVLO Hysteresis CHG_IN OVP Threshold CHG_IN OVP Hysteresis TEST CONDITIONS MIN 4.35 TYP MAX 12 UNIT V V V V mV A CHG_IN Voltage Rising CHG_IN Voltage Falling CHG_IN Voltage Rising CHG_IN Voltage Falling VCHG_IN < VUVLO VCHG_IN < VBAT + 120mV , VCHG_IN > VUVLO VCHG_IN > VBAT + 120mV , VCHG_IN > VUVLO Charger disabled, ISYS = 0mA 3.6 3.8 0.8 6.8 350 20 4.0 CHG_IN Supply Current 50 120 1.8 0.4 200 A mA CHG_IN to VSYS On-Resistance CHG_IN to VSYS Current Limit IVSYS = 100mA ACIN = VSYS ACIN = GA, CHGLEV = GA ACIN = GA, CHGLEV = VSYS 1.5 85 400 0.6 3 105 500 A mA 2 95 450 VSYS AND DCCC REGULATION VSYS Regulated Voltage DCCC Pull-Up Current IVSYS = 10mA VCHG_IN > VBAT + 120mV, Hysteresis = 50mV 4.4 92 4.6 100 4.8 108 V A nSTAT OUTPUT nSTAT Sink current nSTAT Output Low Voltage nSTAT Leakage Current VnSTAT = 2V InSTAT = 1mA VnSTAT = 4.2V 3 5 7 0.4 1 mA V A ACIN AND CHGLEV INPUTS CHGLEV Logic High Input Voltage CHGLEV Logic Low Input Voltage CHGLEV Leakage Current ACIN Logic High Input Voltage ACIN Logic Low Input Voltage ACIN Leakage Current VACIN = 4.2V VCHGLEV = 4.2V 1.4 0.4 1.4 0.4 V V A V V A 1 1 92 0.485 2.47 100 0.500 2.52 30 - 40 - TEMPERATURE SENSE COMPARATOR TH Pull-Up Current VTH Upper Temperature Voltage Threshold (VTHH) VTH Lower Temperature Voltage Threshold (VTHL) VTH Hysteresis Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of Philips Electronics. VCHG_IN > VBAT + 120mV, Hysteresis = 50mV Hot Detect NTC Thermistor Cold Detect NTC Thermistor Upper and Lower 108 0.525 2.57 A V V mV www.active-semi.com Copyright (c) 2009 Active-Semi, Inc. Active-Semi ActivePath ELECTRICAL CHARACTERISTICS CONT'D (VCHG_IN = 5V, TA = 25C, unless otherwise specified.) ACT8810 Rev 4, 01-Oct-09 TM CHARGER PARAMETER CHARGER BAT Reverse Leakage Current BAT to VSYS On-Resistance ISET Pin Voltage TEST CONDITIONS VCHG_IN = 0V, VBAT = 4.2V, IVSYS = 0mA MIN TYP 5 80 MAX UNIT A m Fast Charge Precondition TA = -20C to 70C TA = -40C to 85C ACIN = VSYS, CHGLEV = VSYS ACIN = VSYS, CHGLEV = GA 4.179 4.170 -10% -16% -10% 1.02 0.12 4.2 4.221 4.230 ISET1 50%ISET +10% +16% V V Battery Regulation Voltage Charge Current VBAT = 3.5V ACIN = GA, CHGLEV = VSYS Smallest (450mA or +10% ISET) Smallest (90mA or ISET) 12%ISET 12%ISET 12%ISET Smallest (90mA or 12%ISET) +10% mA ACIN = GA, CHGLEV = GA ACIN = VSYS, CHGLEV = VSYS ACIN = VSYS, CHGLEV = GA Precondition Charge Current VBAT = 2.5V ACIN = GA, CHGLEV = VSYS ACIN = GA, CHGLEV = GA Precondition Threshold Voltage VBAT Voltage Rising -10% mA 2.75 2.85 100 2.95 V mV Precondition Threshold Hysteresis VBAT Voltage Falling ACIN = VSYS, CHGLEV = VSYS End-of-Charge Current Threshold VBAT = 4.2V ACIN = VSYS, CHGLEV = GA ACIN = GA, CHGLEV = VSYS ACIN = GA, CHGLEV = GA Charge Restart Threshold BTR Scale Factor Precondition Safety Timer Fast Charge Safety Timer RBTR = 47k, tPRCHG = 0.24 x RBTR()/180(min) RBTR = 47k, tCHG = 0.24 x RBTR()/60(min) VSET - VBAT, VBAT Falling -10% -10% -10% -10% 150 10%ISET 10%ISET 5%ISET 5%ISET 170 0.24 1 3 +10% +10% +10% +10% 190 mV s/ hr hr mA THERMAL REGULATION Thermal Regulation Threshold : ISET = 640 x (1V/RISET) 100 145 C Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of Philips Electronics. - 41 - www.active-semi.com Copyright (c) 2009 Active-Semi, Inc. Active-Semi ActivePath TYPICAL PERFORMANCE CHARACTERISTICS (VCHG_IN = 5V, RDCCC = 20k, RISET = 680, TA = 25C, unless otherwise specified.) SYS Output Voltage vs. DC Voltage 4.8 4.7 4.25 ACT8810-018 ACT8810 Rev 4, 01-Oct-09 TM CHARGER SYS Voltage vs. SYS Current ACT8810-019 SYS Voltage (V) 4.5 4.4 4.3 4.2 4.1 4.0 0 2 4 6 8 10 ISYS = 10mA 12 14 SYS Voltage (V) 4.6 4.15 4.05 3.95 3.85 VBAT = 4.2V 0 1000 2000 3000 3.75 CHG_IN Voltage (V) SYS Current (mA) Charger Current vs. Battery Voltage (USB Mode) 100 ACT8810-020 Charger Current vs. Battery Voltage (USB Mode) 500 450 Battery Voltage Falling ACT8810-021 Charger Current (mA) Charger Current (mA) 80 VBAT Falling 400 350 300 250 200 150 100 50 60 Battery Voltage Rising 40 VBAT Rising 20 0 0 0.5 1.0 1.5 2.0 2.5 CHG_IN = 5V ISYS = 0mA 100mA USB 3.0 3.5 4.0 4.5 0 0.0 CHG_IN = 5V ISYS = 0mA 500mA USB 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 Battery Voltage (V) Battery Voltage (V) Charger Current vs. Battery Voltage (AC Mode) 1200 1000 ACT8810-022 ISYS = 0mA Battery Voltage Falling Fast Charge Current vs. Ambient Temperature 1200 ACT8810-023 Fast Charger Current (mA) 1000 ACIN, CHGLEV = 11 800 ACIN, CHGLEV = 10 600 400 ACIN, CHGLEV = 01 200 0 ACIN, CHGLEV = 00 Charger Current (mA) 800 Battery Voltage Rising 600 400 200 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 -40 -20 0 20 40 60 80 100 120 140 Battery Voltage (V) Ambient Temperature (C) Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of Philips Electronics. - 42 - www.active-semi.com Copyright (c) 2009 Active-Semi, Inc. Active-Semi ActivePath TYPICAL PERFORMANCE CHARACTERISTICS CONT'D (VCHG_IN = 5V, RDCCC = 20k, RISET = 680, TA = 25C, unless otherwise specified.) ACT8810 Rev 4, 01-Oct-09 TM CHARGER VAC Applied, CHGLEV = LOW ACT8810-024 CH1 CH2 CH1 CH2 CH3 450mA VAC Applied, CHGLEV = HIGH ACT8810-025 CH3 100mA CH4 CH4 CH1: VUSB, 2.00V/div CH2: VCHG_IN, 2.00V/div CH3: IBAT, 500mA/div CH4: VVAC, 2.00V/div TIME: 400s/div CH1: VUSB, 2.00V/div CH2: VCHG_IN, 2.00V/div CH3: IBAT, 500mA/div CH4: VVAC, 2.00V/div TIME: 400s/div VAC Removed, CHGLEV = LOW ACT8810-026 CH1 CH2 VAC Removed, CHGLEV = HIGH ACT8810-027 CH1 CH2 CH3 450mA CH3 100mA CH4 CH4 CH1: VUSB, 2.00V/div CH2: VCHG_IN, 2.00V/div CH3: IBAT, 500mA/div CH4: VVAC, 2.00V/div TIME: 400s/div CH1: VUSB, 2.00V/div CH2: VCHG_IN, 2.00V/div CH3: IBAT, 500mA/div CH4: VVAC, 2.00V/div TIME: 400s/div Battery Leakage Current vs. Battery Voltage 10 ACT8810-028 Battery Leakage Current (A) 8 6 4 2 No CHG_IN CHGLEV = 0 0 1 2 3 4 5 0 Battery Voltage (V) Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of Philips Electronics. - 43 - www.active-semi.com Copyright (c) 2009 Active-Semi, Inc. Active-Semi ActivePath FUNCTIONAL DESCRIPTION General Description The ACT8810 incorporates Active-Semi's patentpending ActivePath architecture. ActivePath is a complete battery-charging and system powermanagement solution for portable hand-held equipment. This circuitry performs a variety of advanced battery-management functions, including automatic selection of the best available input supply, current-management to ensure system power availability, and a complete, high-accuracy (0.5%), thermally regulated, full-featured singlecell linear Li+ charger with an integrated 12V power MOSFET. ACT8810 Rev 4, 01-Oct-09 TM CHARGER System Configuration Optimization ActivePath circuitry automatically detects the state of the input supply, the battery, and the system, and automatically reconfigures itself to optimize the power system. If the input supply is present, ActivePath powers the system in parallel with charging the battery, so that system power and charge current can be independently managed to satisfy all system power requirements. This allows the battery to charge as quickly as possible, while ensuring that the total system current does not exceed the capability of the input supply. If the input supply is not present, however, then ActivePath automatically configures the system to draw power from the battery. Finally, if the input is present and the system current requirement exceeds the capability of the input supply, such as under momentary peak-power consumption conditions, ActivePath automatically configures itself for maximum power capability by drawing system power from both the battery and the input supply. Battery Management Input Protection ActivePath includes a full-featured battery charger for single-cell Li-based batteries. This charger is a full-featured, intelligent, linear-mode, single-cell charger for Lithium-based cells, and was designed specifically to provide a complete charging solution with minimum system design effort. The core of the ActivePath's charger is a CC/CV (Constant-Current/Constant-Voltage), linear-mode charge controller. This controller incorporates current and voltage sense circuitry, an internal 80m power MOSFET, a full-featured statemachine that implements charge control and safety features, and circuitry that eliminates the reverseblocking diode required by conventional charger designs. This charger also features thermal-regulation circuitry that protects it against excessive junction temperature, allowing the fastest possible charging times, as well as proprietary input protection circuitry that makes the charger robust against input voltage transients that can damage other chargers. The charge termination voltage is highly accurate (0.5%), and features a selection of charge safety timeout periods that protect the system from operation with damaged cells. Other features include pin-programmable fast-charge current and - 44 www.active-semi.com Copyright (c) 2009 Active-Semi, Inc. ActivePath Architecture Active-semi's patent-pending ActivePath architecture performs three important functions: 1) Input Protection, 2) System Configuration Optimization, and 3) Battery-Management At the input of the ACT8810's ActivePath circuit is an internal, low-dropout linear regulator (LDO) that regulates the system voltage (VSYS). This LDO features a 12V power MOSFET, allowing the ActivePath system to withstand input voltages of up to 12V, and additionally includes a variety of other protection features, including current limit protection and input over-voltage protection. The ActivePath circuitry provides a very simple means of implementing a solution that safely operates within the current-capability limitations of a USB port while taking advantage of the high outputcurrent capability of an AC adapter, when available. ActivePath limits the total current drawn from the input supply to a value set by the ACIN input; when ACIN is driven to a logic-low ActivePath operates in "USB Mode" and limits the current to either 500mA (when CHGLEV is driven to a logic-high) or to 100mA (when CHGLEV is driven to a logic-low), and when ACIN is driven to a logic-high ActivePath operates in "AC-Mode" and limits the input current to 2A. In either case, ActivePath's DCCC circuitry, described below, allows the input overload protection to be adjusted to accommodate a wide range of input supplies. Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of Philips Electronics. Active-Semi ActivePath FUNCTIONAL DESCRIPTION CONT'D two current-limited nSTAT outputs that can directly drive LED indicators or provide a logic-level status signal to the host microprocessor. ACT8810 Rev 4, 01-Oct-09 TM CHARGER Dynamic Charge Current Control (DCCC) The ACT8810's ActivePath charger features Dynamic Charge Current Control (DCCC) circuitry, which continuously monitors the input supply and prevents input overload conditions by dynamically adjusting the charge current to keep the input voltage from dropping below the DCCC voltage threshold. By default, the DCCC voltage threshold is set to 4.4V, but it may also be programmed by connecting a resistor from DCCC to GA, where the resistor has value given by the following equation: VDCCC = 2 x (IDCCC x RDCCC) (2) Where RDCCC is the value of the external resistor, and IDCCC is the value of the current sourced from DCCC, typically 100A. When ACIN is driven to a logic-low, the circuitry operates in "USB-Mode", which maximum charge current setting of CHGLEV is driven to a logic-high, or CHGLEV is driven to a logic-low. The ACT8810's charge current summarized in the table below: Table 19: ACIN and CHGLEV Inputs Table ACIN CHGLEV 0 0 1 1 0 1 0 1 CHARGE CURRENT ICHG (mA) 90mA or ISET (Smallest one) 450mA or ISET (Smallest one) 50% x ISET ISET ActivePath enforces a 500mA, if 100mA, if are settings PRECONDITION CHARGE CURRENT ICHG (mA) 90mA or 12%ISET (Smallest one) 12% x ISET 12% x ISET 12% x ISET Charger Current Programming The ACT8810's ActivePath charger features a flexible charge current-programming scheme that combines the convenience of internal charge current programming with the flexibility of resistor based charge current programming. Current limits and charge current programming are managed as a function of the ACIN and CHGLEV pins, in combination with RISET, the resistance connected to the ISET pin. ACIN and CHGLEV Inputs ACIN is a logic input that configures the current-limit of ActivePath's linear regulator as well as that of the battery charger. ACIN features a precise 1.25V logic threshold, so that the input voltage detection threshold may be adjusted with a simple resistive voltage divider. This input also allows a simple, lowcost dual-input charger switch to be implemented with just a few, low-cost components. When ACIN is driven to a logic high, the ActivePath operates in "AC-Mode" and the charger charges at the current programmed by RISET, ICHG = 1V/RISET x KISET (3) where KISET = 640 when CHGLEV is driven to a logic high, and K = 320 when CHGLEV is driven to a logic low. Innovative Power TM Note that the actual charging current may be limited to a current that is lower than the programmed fast charge current due to the ACT8810's internal thermal regulation loop. See the Thermal Regulation and Protection section for more information. Battery Temperature Monitoring The ACT8810 continuously monitors the temperature of the battery pack by sensing the resistance of its thermistor, and suspends charging if the temperature of the battery pack exceeds the safety limits. In a typical application, shown in Figure 11, the TH pin is connected to the battery pack's thermistor input. The ACT8810 injects a 100A current out of the TH pin into the thermistor, so that the thermistor resistance is monitored by comparing the voltage at TH to the internal VTHH and VTHL thresholds of 0.5V and 2.5V, respectively. When VTH > VTHL or VTH < VTHH charging and the charge timers are suspended. When VTH returns to the normal range, charging and the charge timers resume. The net resistance from TH to G required to cross the threshold is given by: 100A x RNOM x kHOT = 0.5V RNOM x kHOT = 5k 100A x RNOM x kCOLD = 2.5V RNOM x kCOLD = 25k - 45 www.active-semi.com Copyright (c) 2009 Active-Semi, Inc. ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of Philips Electronics. Active-Semi ActivePath FUNCTIONAL DESCRIPTION CONT'D where RNOM is the nominal thermistor resistance at room temperature, and kHOT and kCOLD are the ratios of the thermistor's resistance at the desired hot and cold thresholds, respectively. Figure 11: Simple Configuration ACT8810 100A + - ACT8810 Rev 4, 01-Oct-09 TM CHARGER Simple Solution The ACT8810 was designed to accommodate most requirements with very little design effort, but also provides flexibility when additional control over a design is required. Initial thermistor selection is accomplished by choosing one that best meets the following requirements: RNOM = 5k/kHOT, and RNOM = 25k/kCOLD where kHOT and kCOLD for a given thermistor can be found on its characteristic tables. Taking a 0C to 40C application using a "curve 2" NTC for this example, from the characteristic tables one finds that kHOT and kCOLD are 0.5758 and 2.816, respectively, and the RNOM that most closely satisfies these requirements is therefore around 8.8k. Selecting 10k as the nearest standard value, calculate kCOLD and kHOT as: kCOLD = VTHL/(ITH x RNOM) = 2.5V/(100A x 10k) = 2.5 kHOT = VTHH/(ITH x RNOM) = 0.5V/(100A x 10k) = 0.5 Identifying these values on the curve 2 characteristic tables indicates that the resulting operating temperature range is 2C to 44C, vs. the design goal of 0C to 40C. This example demonstrates that one can satisfy common operating temperature ranges with very little design effort. Fix VTHH For demonstration purposes, supposing that we had selected the next closest standard thermistor value of 6.8k in the example above, we would have obtained the following results: kCOLD = VTHL/(ITH x RNOM) = 2.5V/(100A x 6.8k) = 3.67 kHOT = VTHH/(ITH x RNOM) = 0.5V/(100A x 6.8k) = 0.74 which, according to the characteristic tables would have resulted in an operating temperature range of -6C to 33C vs. the design goal of 0C to 40C. In this case, one can add resistance in series with the thermistor to shift the range upwards, using the following equation: (VTHH/ITH) = kHOT(@40C) x RNOM + R R = (VTHH/ITH) - kHOT(@40C) x RNOM R = (2.5V/100A) - 0.5758 x 6.8k - 46 www.active-semi.com Copyright (c) 2009 Active-Semi, Inc. VTHH TH + Li+ Battery Pack + - NTC VTHL - Design Procedure When designing with thermistors it is important to keep in mind that their nonlinear behavior typically allows one to directly control no more than one threshold at a time. As a result, the design procedure can change depending on which threshold is most critical for a given application. Most application requirements can be solved using one of three cases, 1) Simple solution 2) Fix VTHH, accept the resulting VTHL 3) Fix VTHL, accept the resulting VTHH The ACT8810 was designed to achieve an operating temperature range that is suitable for most applications with very little design effort. The simple solution is often found to provide reasonable results and should always be used first, then the design procedure may proceed to one of the other solutions if necessary. In each design example, we refer to the Vishay NTHS series of NTCs, and more specifically those which follow a "curve 2" characteristic. For more information on these NTCs, as well as access to the resistance/temperature characteristic tables referred to in the example, please refer to the Vishay website at http://www.vishay.com/thermistors. Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of Philips Electronics. Active-Semi ActivePath FUNCTIONAL DESCRIPTION CONT'D Finally, R = 5k - 3.9k = 1.1k This result shows that adding 1.1k in series with the thermistor sets the net resistance from TH to G to be 0.5V at 40C, satisfying VTHH at the correct temperature. Adding this resistance, however, also impacts the lower temperature limit as follows: VTHL/ITH = kCOLD(@TC) x RNOM + R kCOLD(@TC) = (VTHL/ITH) - R)/RNOM Finally, kCOLD(@TC) = (25k - 1.1k)/6.8k = 3.51 Reviewing the characteristic curves, the lower threshold is found to move to -5C, a change of only 1C. As a result, the system satisfies the upper threshold of 40C with an operating temperature range of -5C to 40C, vs. our design target of 0C to 40C. It is informative to highlight that due to the NTC behavior of the thermistor, the relative impact on the lower threshold is significantly smaller than the impact on the upper threshold. ACT8810 Rev 4, 01-Oct-09 TM CHARGER at low temperatures by connecting a resistor in parallel with ITH. The desired resistance can be found using the following equation: (ITH + (VCHG_IN - VTHL)/R) x kCOLD(@0C) x RNOM = VTHL Rearranging yields R = (VCHG_IN - VTHL)/(VTHL/(kCOLD(@0C) x RNOM) - ITH) R = (5V - 2.5V)/(2.5V/(2.816 x 6.8k) - 100A) R = 82k Adding 82k in parallel with the current source increases the net current flowing into the thermistor, thus increasing the voltage at TH. Adding this resistance, however, also impacts the upper temperature limit: VTHH = (ITH + (VCHG_IN - VTHH)/R) x kHOT(@40C) x RNOM Rearranging yields, kHOT(@TC) = VTHH/(RNOM x (ITH + (VCHG_IN - VTHH)/R)) kHOT(@TC) = 0.5V/(6.8k x (100A + (5V - 0.5V)/82k)) = 0.4748 Reviewing the characteristic curves, the upper threshold is found to move to 45C, a change of about 14C. Adding the parallel resistance has allowed us to achieve our desired lower threshold of 0C with an operating temperature range of 0C to 45C, vs. our design target of 0C to 40C. Fix VTHL Following the same example as above, the "unadjusted" results yield an operating temperature range of -6C to 33C vs. the design goal of 0C to 40C. In applications that favor VTHL over VTHH, however, one can control the voltage present at TH Figure 12: Fix VTHH Configuration Figure 13: Fix VTHL Configuration ACT8810 100A + - ACT8810 100A + CHG_IN + VTHH TH R Li+ Battery Pack + - VTHH TH R Li+ Battery Pack + - NTC VTHL - + - NTC VTHL - Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of Philips Electronics. - 47 - www.active-semi.com Copyright (c) 2009 Active-Semi, Inc. Active-Semi ActivePath FUNCTIONAL DESCRIPTION CONT'D Thermal Regulation The ACT8810's ActivePath charger features an internal thermal regulation loop that reduces the charging current as necessary to ensure that the die temperature does not rise beyond the thermal regulation threshold of 110C. This feature protects the against excessive junction temperature and makes the device more accommodating to aggressive thermal designs. Note, however, that attention to good thermal designs is required to achieve the fastest possible charge time by maximizing charge current. In order to account for the reduced charge current resulting from operation in thermal regulation mode, the charge timeout periods are extended proportionally to the reduction in charge current. Table 20: ACT8810 Rev 4, 01-Oct-09 TM CHARGER Charging Status Indication Table STATE Charging Discharging Charging Complete Input Floating Fault nSTAT ON OFF OFF OFF OFF Input Supply Detection The ACT8810's ActivePath charger is capable of withstanding voltages of up to 12V, protecting the system from fault conditions such as input voltage transients or application of an incorrect input supply. Although the ACT8810 can withstand a wide range of input voltages, valid input voltages for charging must be greater than the under-voltage lockout voltage (UVLO) and the over-voltage protection (OVP) thresholds, as described below. Under Voltage Lock Output (UVLO) Whenever the input voltage applied to CHG_IN falls below 3.0V (typ), an input under-voltage condition is detected and the charger is disabled. Once an input under-voltage condition is detected, the input must exceed the under-voltage threshold by at least 800mV for charging to resume. Over Voltage Protection (OVP) If the charger detects that the voltage applied to CHG_IN exceeds 6.8V (typ), an over-voltage condition is detected and the charger is disabled. Once an input over-voltage condition is detected, the input must fall below the OVP threshold by at least 350mV for charging to resume. Charging Safety Timers The ACT8810 features a safety timer that is programmable via an external resistor (RBTR) connected from BTR to GA. The timeout period is calculated as a function of this resistor by the following equation: tCHG = KBTR x RBTR, where KBTR = 0.24s/. If the timeout period expires prior to charge termination, the charger is disabled and the nSTAT pin signal a fault condition. If the ACT8810 detects that the charger remains in precondition for longer than the precondition time out period (which determined as tCHG/3), the ACT8810 turns off the charger and generate a FAULT to ensure prevent charging a bad cell. Charging Status Indication The ACT8810 provides one charge-status output, nSTAT which indicates charge status as defined in Table 20. nSTAT is open-drain output with internal 5mA current limits, which sinks current when asserted and are high-Z otherwise, and is capable of directly driving LED without the need of currentlimiting resistor or other external circuitry. To drive an LED, simply connect the LED between nSTAT pin and an appropriate supply (typically VSYS). For a logic level indication, simply connect a resistor from nSTAT to a appropriate voltage supply. Reverse Leakage Current The ACT8810's ActivePath charger includes internal circuitry that eliminates the need for blocking diodes, reducing solution size and cost as well as dropout voltage relative to conventional battery chargers. When the voltage at CHG_IN falls below VBAT, the charger automatically reconfigures its power switch to minimize current drain from the battery. Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of Philips Electronics. - 48 - www.active-semi.com Copyright (c) 2009 Active-Semi, Inc. Active-Semi ActivePath Figure 14: Typical Li+ charge profile and ACT8810 charge states VSET RECHARGE ISET Current Voltage VPRECHARGE ACT8810 Rev 4, 01-Oct-09 TM CHARGER 12% ISET STATE A B C D E B A: PRECONDITION State B: FAST-CHARGE State C: TOP-OFF State D: SLEEP State E: DISCHARGE State Figure 15: Charger State Diagram ANY STATE BATTERY REMOVED OR VCHG_IN < VBAT + 120mV OR VCHG_IN < UVLO SUSPEND BATTERY REPLACED AND VCHG_IN > VBAT + 120mV AND VCHG_IN > UVLO T > TPRECONDITION AND VBAT < 2.85V TIMEOUT-FAULT PRECONDITION VBAT > 2.85V T > TNORMAL AND VBAT < VTERM FAST-CHARGE VBAT = VTERM TOP-OFF IBAT < ITERM IBAT > ITERM DELAY SLEEP VBAT < VTERM - 175mV Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of Philips Electronics. - 49 - www.active-semi.com Copyright (c) 2009 Active-Semi, Inc. Active-Semi ActivePath FUNCTIONAL DESCRIPTION CONT'D Charger State-Machine PRECONDITION State A new charging cycle begins with the PRECONDITION state, and operation continues in this state until VBAT exceeds the Precondition Threshold Voltage of 2.85V (typ). When operating in PRECONDITION state, the cell is charged at a reduced current, 12% of the programmed maximum fast-charge constant current, ISET. Once VBAT reaches the Precondition Threshold Voltage the state machine jumps to the NORMAL state. If VBAT does not reach the Precondition Threshold Voltage before the Precondition Timeout period tPRECONDITION expires, then a damaged cell is detected and the state machine jumps to the TIMEOUT-FAULT State. For the Precondition Timeout period, see the Charging Safety Timers section for more information. FAST CHARGE State Normal state is made up of two operating modes, fast charge Constant-Current (CC) and ConstantVoltage (CV). In CC mode, the ACT8810 charges at the current programmed by RISET (see the Current Limits and Charge Current Programming section for more information). During a normal charge cycle fast-charge continues in CC mode until VBAT reaches the charge termination voltage (VTERM), at which point the ACT8810 charges in CV mode. Charging continues in CV mode until the charge current drops to 10% (ACIN = 1) or 5% (ACIN = 0) of the programmed maximum charge current, at which point the state machine jumps to the TOPOFF state. If VBAT does not proceed out of the NORMAL state before the Normal Timeout period (TNORMAL) expires, then a damaged cell is detected and the state machine jumps to the TIMEOUTFAULT State. See the Charging Safety Times section for more information. TOP-OFF State In the TOP-OFF state, the cell is charged in constant-voltage (CV) mode. Charge current decreases as charging continues. During a normal charging cycle charging proceeds until the charge current decreases below the End-Of-Charge (EOC) threshold, defined as 10% of ISET (ACIN = 1) or 5% of ISET (ACIN = 0) . When this happens, the state machine terminates the charge cycle and jumps to the SLEEP state. Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of Philips Electronics. ACT8810 Rev 4, 01-Oct-09 TM CHARGER End of Charge State In the End-of-Charge (EOC) state, the ACT8810 presents a high-impedance to the battery, allowing the cell to "relax" and minimizes battery leakage current. The ACT8810 continues to monitor the cell voltage, however, so that it can re-initiate charging cycles as necessary to ensure that the cell remains fully charged. SUSPEND State The ACT8810 features an user-selectable suspendcharge mode, which disables the charger but keeps other circuiting functional. The charger can be put into suspend mode by driving EN to logic low. Upon exiting the SUSPEND State, the charge timer is reset and the state machine jumps to PRECONDITION state. SLEEP State In SLEEP mode the ACT8810 presents a highimpedance to the battery, allowing the cell to "relax" and minimizes battery leakage current. The ACT8810 continues to monitor the cell voltage, however, so that it can re-initiate charging as necessary to ensure that the cell remains fully charged. Under normal operation, the state machine initiates a new charging cycle by jumping to the FAST-CHARGE state when VBAT drops below the Charge Termination Threshold. CHG_IN Bypass Capacitor Selection CHG_IN is the power input for the ACT8810 battery charger. The battery charger is automatically enabled whenever a valid voltage is present on CHG_IN. In most applications, CHG_IN is connected to either a wall adapter or USB port. Under normal operation, the input of the charger will often be "hot-plugged" directly to a powered USB or wall adapter cable, and supply voltage ringing and overshoot may appear at the CHG_IN pin. In most applications a high quality capacitor connected from CHG_IN to GA, placed as close as possible to the IC, is sufficient to absorb the energy. Wall-adapter powered applications provide flexibility in input capacitor selection, but the USB specification presents limitations to input capacitance selection. In order to meet both the USB 2.0 and USB OTG (On The Go) specifications while avoiding USB supply under-voltage conditions - 50 - www.active-semi.com Copyright (c) 2009 Active-Semi, Inc. Active-Semi ActivePath FUNCTIONAL DESCRIPTION CONT'D resulting from the current limit slew rate (100mA/S) limitations of the USB bus, the CHG_IN bypass capacitance value must to be between 4.7F and 10F for the ACT8810. Ceramic capacitors are often preferred for bypassing applications due to their small size and good surge current ratings, but care must be taken in applications that can encounter hot plug conditions as their very low ESR, in combination with the inductance of the cable, can create a highQ filter that induces excessive ringing at the CHG_IN pin. This ringing can couple to the output and be mistaken as loop instability, or the ringing may be large enough to damage the input itself. Although the CHG_IN pin is designed for maximum ACT8810 Rev 4, 01-Oct-09 TM CHARGER robustness and an absolute maximum voltage rating of 14V for transients, attention must be given to bypass techniques to ensure safe operation. As a result, design of the CHG_IN bypass must take care to "de-Q" the filter. This can be accomplished by connecting a 1 resistor in series with a ceramic capacitor (as shown in Figure 16), or by using a tantalum or electrolytic capacitor to utilize it's higher ESR to dampen the ringing. For additional protection in extreme situations, Zener diodes with 12V clamp voltages may also be used. In any case, it is always critical to evaluate voltage transients at the ACT8810 CHG_IN pin with an oscilloscope to ensure safe operation. Figure 16: CHG_IN Bypass Options for USB or Wall Adaptor Supplies Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of Philips Electronics. - 51 - www.active-semi.com Copyright (c) 2009 Active-Semi, Inc. Active-Semi ACT8810 Rev 4, 01-Oct-09 PACKAGE OUTLINE AND DIMENSIONS PACKAGE OUTLINE TQFN55-40 PACKAGE OUTLINE AND DIMENSIONS D D/2 SYMBOL A E/2 DIMENSION IN MILLIMETERS MIN 0.700 DIMENSION IN INCHES MIN 0.028 MAX 0.800 MAX 0.031 A1 E 0.200 REF 0.000 0.150 4.900 4.900 3.450 3.450 0.050 0.250 5.100 5.100 3.750 3.750 0.008 REF 0.000 0.006 0.193 0.193 0.136 0.136 0.002 0.010 0.201 0.201 0.148 0.148 A2 b D E D2 E2 A A1 D2 L b A2 e L R 0.400 BSC 0.300 0.500 0.016 BSC 0.012 0.020 0.300 0.012 e E2 R Active-Semi, Inc. reserves the right to modify the circuitry or specifications without notice. Users should evaluate each product to make sure that it is suitable for their applications. Active-Semi products are not intended or authorized for use as critical components in life-support devices or systems. Active-Semi, Inc. does not assume any liability arising out of the use of any product or circuit described in this datasheet, nor does it convey any patent license. Active-Semi and its logo are trademarks of Active-Semi, Inc. For more information on this and other products, contact sales@active-semi.com or visit http://www.active-semi.com. For other inquiries, please send to: 2728 Orchard Parkway, San Jose, CA 95134-2012, USA Innovative PowerTM ActivePMUTM and ActivePathTM are trademarks of Active-Semi. I2CTM is a trademark of Philips Electronics. - 52 - www.active-semi.com Copyright (c) 2009 Active-Semi, Inc. |
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